1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/clock/ra_clock.h>
8#include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
9
10/ {
11	soc {
12		sram0: memory@1ffe0000 {
13			compatible = "mmio-sram";
14			reg = <0x1ffe0000 DT_SIZE_K(256)>;
15		};
16
17		flash-controller@407e0000 {
18			reg = <0x407e0000 0x1000>;
19			#address-cells = <1>;
20			#size-cells = <1>;
21
22			flash0: flash@0 {
23				compatible = "soc-nv-flash";
24				reg = <0x0 DT_SIZE_K(512)>;
25			};
26		};
27
28		trng: trng {
29			compatible = "renesas,ra-sce7-rng";
30			status = "disabled";
31		};
32
33		adc@4005c000 {
34			channel-count = <11>;
35			channel-available-mask = <0x1700ef>;
36		};
37
38		adc@4005c200 {
39			channel-count = <8>;
40			channel-available-mask = <0x300e7>;
41		};
42	};
43
44	clocks: clocks {
45		#address-cells = <1>;
46		#size-cells = <1>;
47
48		xtal: clock-main-osc {
49			compatible = "renesas,ra-cgc-external-clock";
50			clock-frequency = <DT_FREQ_M(12)>;
51			#clock-cells = <0>;
52			status = "disabled";
53		};
54
55		hoco: clock-hoco {
56			compatible = "fixed-clock";
57			clock-frequency = <DT_FREQ_M(20)>;
58			#clock-cells = <0>;
59		};
60
61		moco: clock-moco {
62			compatible = "fixed-clock";
63			clock-frequency = <DT_FREQ_M(8)>;
64			#clock-cells = <0>;
65		};
66
67		loco: clock-loco {
68			compatible = "fixed-clock";
69			clock-frequency = <32768>;
70			#clock-cells = <0>;
71		};
72
73		subclk: clock-subclk {
74			compatible = "renesas,ra-cgc-subclk";
75			clock-frequency = <32768>;
76			#clock-cells = <0>;
77			status = "disabled";
78		};
79
80		pll: pll {
81			compatible = "renesas,ra-cgc-pll";
82			#clock-cells = <0>;
83
84			/* PLL */
85			clocks = <&xtal>;
86			div = <1>;
87			mul = <20 0>;
88			status = "disabled";
89		};
90
91		pclkblock: pclkblock@4001e01c {
92			compatible = "renesas,ra-cgc-pclk-block";
93			reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
94			      <0x40047008 4>;
95			reg-names = "MSTPA", "MSTPB","MSTPC",
96				    "MSTPD";
97			#clock-cells = <0>;
98			clocks = <&pll>;
99			status = "okay";
100
101			iclk: iclk {
102				compatible = "renesas,ra-cgc-pclk";
103				div = <2>;
104				#clock-cells = <2>;
105				status = "okay";
106			};
107
108			pclka: pclka {
109				compatible = "renesas,ra-cgc-pclk";
110				div = <2>;
111				#clock-cells = <2>;
112				status = "okay";
113			};
114
115			pclkb: pclkb {
116				compatible = "renesas,ra-cgc-pclk";
117				div = <4>;
118				#clock-cells = <2>;
119				status = "okay";
120			};
121
122			pclkc: pclkc {
123				compatible = "renesas,ra-cgc-pclk";
124				div = <4>;
125				#clock-cells = <2>;
126				status = "okay";
127			};
128
129			pclkd: pclkd {
130				compatible = "renesas,ra-cgc-pclk";
131				div = <2>;
132				#clock-cells = <2>;
133				status = "okay";
134			};
135
136			bclk: bclk {
137				compatible = "renesas,ra-cgc-pclk";
138				div = <2>;
139				bclkout: bclkout {
140					compatible = "renesas,ra-cgc-busclk";
141					clk-out-div = <2>;
142					sdclk = <0>;
143					#clock-cells = <0>;
144				};
145				#clock-cells = <2>;
146				status = "okay";
147			};
148
149			uclk: uclk {
150				compatible = "renesas,ra-cgc-pclk";
151				div = <5>;
152				#clock-cells = <2>;
153				status = "okay";
154			};
155
156			fclk: fclk {
157				compatible = "renesas,ra-cgc-pclk";
158				div = <4>;
159				#clock-cells = <2>;
160				status = "okay";
161			};
162
163			clkout: clkout {
164				compatible = "renesas,ra-cgc-pclk";
165				#clock-cells = <2>;
166				status = "disabled";
167			};
168		};
169	};
170};
171
172&ioport0 {
173	port-irqs = <&port_irq6 &port_irq7 &port_irq8
174	&port_irq9 &port_irq10 &port_irq11
175	&port_irq12 &port_irq13>;
176	port-irq-names = "port-irq6",
177			 "port-irq7",
178			 "port-irq8",
179			 "port-irq9",
180			 "port-irq10",
181			 "port-irq11",
182			 "port-irq12",
183			 "port-irq13";
184	port-irq6-pins = <0>;
185	port-irq7-pins = <1>;
186	port-irq8-pins = <2>;
187	port-irq9-pins = <4>;
188	port-irq10-pins = <5>;
189	port-irq11-pins = <6>;
190	port-irq12-pins = <8>;
191	port-irq13-pins = <15>;
192};
193
194&ioport1 {
195	port-irqs = <&port_irq0 &port_irq1 &port_irq2
196	&port_irq3 &port_irq4>;
197	port-irq-names = "port-irq0",
198			 "port-irq1",
199			 "port-irq2",
200			 "port-irq3",
201			 "port-irq4";
202	port-irq0-pins = <5>;
203	port-irq1-pins = <1 4>;
204	port-irq2-pins = <0>;
205	port-irq3-pins = <10>;
206	port-irq4-pins = <11>;
207};
208
209&ioport2 {
210	port-irqs = <&port_irq0 &port_irq1 &port_irq2
211	&port_irq3>;
212	port-irq-names = "port-irq0",
213			 "port-irq1",
214			 "port-irq2",
215			 "port-irq3";
216	port-irq0-pins = <6>;
217	port-irq1-pins = <5>;
218	port-irq2-pins = <13>;
219	port-irq3-pins = <12>;
220};
221
222&ioport3 {
223	port-irqs = <&port_irq5 &port_irq6
224	&port_irq8 &port_irq9>;
225	port-irq-names = "port-irq5",
226			 "port-irq6",
227			 "port-irq8",
228			 "port-irq9";
229	port-irq5-pins = <2>;
230	port-irq6-pins = <1>;
231	port-irq8-pins = <5>;
232	port-irq9-pins = <4>;
233};
234
235&ioport4 {
236	port-irqs = <&port_irq0 &port_irq4 &port_irq5
237	&port_irq6 &port_irq7 &port_irq8
238	&port_irq9>;
239	port-irq-names = "port-irq0",
240			 "port-irq4",
241			 "port-irq5",
242			 "port-irq6",
243			 "port-irq7",
244			 "port-irq8",
245			 "port-irq9";
246	port-irq0-pins = <0>;
247	port-irq4-pins = <2 11>;
248	port-irq5-pins = <1 10>;
249	port-irq6-pins = <9>;
250	port-irq7-pins = <8>;
251	port-irq8-pins = <15>;
252	port-irq9-pins = <14>;
253};
254
255&ioport5 {
256	port-irqs = <&port_irq11 &port_irq12>;
257	port-irq-names = "port-irq11",
258			 "port-irq12";
259	port-irq11-pins = <1>;
260	port-irq12-pins = <2>;
261};
262
263&ioport7 {
264	port-irqs = <&port_irq11>;
265	port-irq-names = "port-irq11";
266	port-irq11-pins = <8>;
267};
268