1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  PLL node binding for STM32L4 and STM32L5 devices
6
7  It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2.
8  Only main PLL is supported for now.
9
10  These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
11  an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
12  clock in this acceptable range.
13
14  Each PLL can have up to 3 output clocks and for each output clock, the
15  frequency can be computed with the following formulae:
16
17    f(PLL_P) = f(VCO clock) / PLLP  --> PLLSAI3CLK
18    f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48M1CLK
19    f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)
20
21      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
22
23  The PLL output frequency must not exceed 80 MHz.
24
25compatible: "st,stm32l4-pll-clock"
26
27include: [clock-controller.yaml, base.yaml]
28
29properties:
30  "#clock-cells":
31    const: 0
32
33  clocks:
34    required: true
35
36  div-m:
37    type: int
38    required: true
39    description: |
40        Division factor for the main PLL and audio PLLs (PLLSAI1 and PLLSAI2)
41        input clock
42        Valid range: 1 - 8
43
44  mul-n:
45    type: int
46    required: true
47    description: |
48        Main PLL multiplication factor for VCO
49        Valid range: 8 - 86
50
51  div-p:
52    type: int
53    description: |
54        Main PLL division factor for PLLSAI3CLK
55    enum:
56      - 7
57      - 17
58
59  div-q:
60    type: int
61    description: |
62        Main PLL division factor for PLL48M1CLK (48 MHz clock).
63    enum:
64      - 2
65      - 4
66      - 6
67      - 8
68
69  div-r:
70    type: int
71    required: true
72    description: |
73        Main PLL division factor for PLLCLK (system clock)
74    enum:
75      - 2
76      - 4
77      - 6
78      - 8
79