1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/renesas/ra/ra8/ra8x1.dtsi>
8#include <zephyr/dt-bindings/clock/ra_clock.h>
9
10/ {
11	clocks: clocks {
12		#address-cells = <1>;
13		#size-cells = <1>;
14
15		xtal: clock-main-osc {
16			compatible = "renesas,ra-cgc-external-clock";
17			clock-frequency = <DT_FREQ_M(24)>;
18			#clock-cells = <0>;
19			status = "disabled";
20		};
21
22		hoco: clock-hoco {
23			compatible = "fixed-clock";
24			clock-frequency = <DT_FREQ_M(48)>;
25			#clock-cells = <0>;
26		};
27
28		moco: clock-moco {
29			compatible = "fixed-clock";
30			clock-frequency = <DT_FREQ_M(8)>;
31			#clock-cells = <0>;
32		};
33
34		loco: clock-loco {
35			compatible = "fixed-clock";
36			clock-frequency = <32768>;
37			#clock-cells = <0>;
38		};
39
40		subclk: clock-subclk {
41			compatible = "renesas,ra-cgc-subclk";
42			clock-frequency = <32768>;
43			#clock-cells = <0>;
44			status = "disabled";
45		};
46
47		pll: pll {
48			compatible = "renesas,ra-cgc-pll";
49			#clock-cells = <0>;
50			clocks = <&xtal>;
51			div = <2>;
52			mul = <80 0>;
53
54			pllp: pllp {
55				compatible = "renesas,ra-cgc-pll-out";
56				div = <2>;
57				freq = <DT_FREQ_M(480)>;
58				status = "disabled";
59				#clock-cells = <0>;
60			};
61
62			pllq: pllq {
63				compatible = "renesas,ra-cgc-pll-out";
64				div = <2>;
65				freq = <DT_FREQ_M(480)>;
66				status = "disabled";
67				#clock-cells = <0>;
68			};
69
70			pllr: pllr {
71				compatible = "renesas,ra-cgc-pll-out";
72				div = <2>;
73				freq = <DT_FREQ_M(480)>;
74				status = "disabled";
75				#clock-cells = <0>;
76			};
77			status = "disabled";
78		};
79
80		pll2: pll2 {
81			compatible = "renesas,ra-cgc-pll";
82			#clock-cells = <0>;
83
84			div = <2>;
85			mul = <96 0>;
86
87			pll2p: pll2p {
88				compatible = "renesas,ra-cgc-pll-out";
89				div = <2>;
90				freq = <DT_FREQ_M(0)>;
91				status = "disabled";
92				#clock-cells = <0>;
93			};
94
95			pll2q: pll2q {
96				compatible = "renesas,ra-cgc-pll-out";
97				div = <2>;
98				freq = <DT_FREQ_M(0)>;
99				status = "disabled";
100				#clock-cells = <0>;
101			};
102
103			pll2r: pll2r {
104				compatible = "renesas,ra-cgc-pll-out";
105				div = <2>;
106				freq = <DT_FREQ_M(0)>;
107				status = "disabled";
108				#clock-cells = <0>;
109			};
110			status = "disabled";
111		};
112
113		pclkblock: pclkblock@40203000 {
114			compatible = "renesas,ra-cgc-pclk-block";
115			reg = <0x40203000 4>, <0x40203004 4>, <0x40203008 4>,
116			      <0x4020300c 4>, <0x40203010 4>;
117			reg-names = "MSTPA", "MSTPB","MSTPC",
118				    "MSTPD", "MSTPE";
119			#clock-cells = <0>;
120			clocks = <&pllp>;
121			status = "okay";
122
123			cpuclk: cpuclk {
124				compatible = "renesas,ra-cgc-pclk";
125				div = <1>;
126				#clock-cells = <2>;
127				status = "okay";
128			};
129
130			iclk: iclk {
131				compatible = "renesas,ra-cgc-pclk";
132				div = <2>;
133				#clock-cells = <2>;
134				status = "okay";
135			};
136
137			pclka: pclka {
138				compatible = "renesas,ra-cgc-pclk";
139				div = <4>;
140				#clock-cells = <2>;
141				status = "okay";
142			};
143
144			pclkb: pclkb {
145				compatible = "renesas,ra-cgc-pclk";
146				div = <8>;
147				#clock-cells = <2>;
148				status = "okay";
149			};
150
151			pclkc: pclkc {
152				compatible = "renesas,ra-cgc-pclk";
153				div = <8>;
154				#clock-cells = <2>;
155				status = "okay";
156			};
157
158			pclkd: pclkd {
159				compatible = "renesas,ra-cgc-pclk";
160				div = <4>;
161				#clock-cells = <2>;
162				status = "okay";
163			};
164
165			pclke: pclke {
166				compatible = "renesas,ra-cgc-pclk";
167				div = <2>;
168				#clock-cells = <2>;
169				status = "okay";
170			};
171
172			bclk: bclk {
173				compatible = "renesas,ra-cgc-pclk";
174				div = <4>;
175				bclkout: bclkout {
176					compatible = "renesas,ra-cgc-busclk";
177					clk-out-div = <2>;
178					sdclk = <1>;
179					#clock-cells = <0>;
180				};
181				#clock-cells = <2>;
182				status = "okay";
183			};
184
185			fclk: fclk {
186				compatible = "renesas,ra-cgc-pclk";
187				div = <8>;
188				#clock-cells = <2>;
189				status = "okay";
190			};
191
192			clkout: clkout {
193				compatible = "renesas,ra-cgc-pclk";
194				#clock-cells = <2>;
195				status = "disabled";
196			};
197
198			sciclk: sciclk {
199				compatible = "renesas,ra-cgc-pclk";
200				#clock-cells = <2>;
201				status = "disabled";
202			};
203
204			spiclk: spiclk {
205				compatible = "renesas,ra-cgc-pclk";
206				#clock-cells = <2>;
207				status = "disabled";
208			};
209
210			canfdclk: canfdclk {
211				compatible = "renesas,ra-cgc-pclk";
212				#clock-cells = <2>;
213				status = "disabled";
214			};
215
216			i3cclk: i3cclk {
217				compatible = "renesas,ra-cgc-pclk";
218				#clock-cells = <2>;
219				status = "disabled";
220			};
221
222			uclk: uclk {
223				compatible = "renesas,ra-cgc-pclk";
224				#clock-cells = <2>;
225				status = "disabled";
226			};
227
228			u60clk: u60clk {
229				compatible = "renesas,ra-cgc-pclk";
230				#clock-cells = <2>;
231				status = "disabled";
232			};
233
234			octaspiclk: octaspiclk {
235				compatible = "renesas,ra-cgc-pclk";
236				#clock-cells = <2>;
237				status = "disabled";
238			};
239
240			lcdclk: lcdclk {
241				compatible = "renesas,ra-cgc-pclk";
242				#clock-cells = <2>;
243				status = "disabled";
244			};
245		};
246	};
247};
248
249&ioport0 {
250	port-irqs = <&port_irq6 &port_irq7 &port_irq8
251	&port_irq9 &port_irq10 &port_irq11
252	&port_irq12 &port_irq13 &port_irq14>;
253	port-irq-names = "port-irq6",
254			 "port-irq7",
255			 "port-irq8",
256			 "port-irq9",
257			 "port-irq10",
258			 "port-irq11",
259			 "port-irq12",
260			 "port-irq13",
261			 "port-irq14";
262	port-irq6-pins = <0>;
263	port-irq7-pins = <1>;
264	port-irq8-pins = <2>;
265	port-irq9-pins = <4>;
266	port-irq10-pins = <5>;
267	port-irq11-pins = <6>;
268	port-irq12-pins = <8>;
269	port-irq13-pins = <9 15>;
270	port-irq14-pins = <10>;
271};
272
273&ioport1 {
274	port-irqs = <&port_irq0 &port_irq1 &port_irq2>;
275	port-irq-names = "port-irq0",
276			 "port-irq1",
277			 "port-irq2";
278	port-irq0-pins = <5>;
279	port-irq1-pins = <1 4>;
280	port-irq2-pins = <0>;
281};
282
283&ioport2 {
284	port-irqs = <&port_irq0 &port_irq1 &port_irq2
285	&port_irq3>;
286	port-irq-names = "port-irq0",
287			 "port-irq1",
288			 "port-irq2",
289			 "port-irq3";
290	port-irq0-pins = <6>;
291	port-irq1-pins = <5>;
292	port-irq2-pins = <3 13>;
293	port-irq3-pins = <2 8 12>;
294};
295
296&ioport3 {
297	port-irqs = <&port_irq4 &port_irq5 &port_irq6
298	&port_irq8 &port_irq9>;
299	port-irq-names = "port-irq4",
300			 "port-irq5",
301			 "port-irq6",
302			 "port-irq8",
303			 "port-irq9";
304	port-irq4-pins = <0>;
305	port-irq5-pins = <2>;
306	port-irq6-pins = <1>;
307	port-irq8-pins = <5>;
308	port-irq9-pins = <4>;
309};
310
311&ioport4 {
312	port-irqs = <&port_irq0 &port_irq4 &port_irq5
313	&port_irq6 &port_irq7 &port_irq8
314	&port_irq9 &port_irq14 &port_irq15>;
315	port-irq-names = "port-irq0",
316			 "port-irq4",
317			 "port-irq5",
318			 "port-irq6",
319			 "port-irq7",
320			 "port-irq8",
321			 "port-irq9",
322			 "port-irq14",
323			 "port-irq15";
324	port-irq0-pins = <0>;
325	port-irq4-pins = <2 11>;
326	port-irq5-pins = <1 10>;
327	port-irq6-pins = <9>;
328	port-irq7-pins = <8>;
329	port-irq8-pins = <15>;
330	port-irq9-pins = <14>;
331	port-irq14-pins = <3>;
332	port-irq15-pins = <4>;
333};
334
335&ioport5 {
336	port-irqs = <&port_irq1 &port_irq2 &port_irq3
337	&port_irq14 &port_irq15>;
338	port-irq-names = "port-irq1",
339			 "port-irq2",
340			 "port-irq3",
341			 "port-irq14",
342			 "port-irq15";
343	port-irq1-pins = <8>;
344	port-irq2-pins = <9>;
345	port-irq3-pins = <10>;
346	port-irq14-pins = <12>;
347	port-irq15-pins = <11>;
348};
349
350&ioport6 {
351	port-irqs = <&port_irq7>;
352	port-irq-names = "port-irq7";
353	port-irq7-pins = <15>;
354};
355
356&ioport7 {
357	port-irqs = <&port_irq7 &port_irq8 &port_irq10
358	&port_irq11>;
359	port-irq-names = "port-irq7",
360			 "port-irq8",
361			 "port-irq10",
362			 "port-irq11";
363	port-irq7-pins = <6>;
364	port-irq8-pins = <7>;
365	port-irq10-pins = <9>;
366	port-irq11-pins = <8>;
367};
368
369&ioport8 {
370	port-irqs = <&port_irq0 &port_irq11 &port_irq12
371	&port_irq14 &port_irq15>;
372	port-irq-names = "port-irq0",
373			 "port-irq11",
374			 "port-irq12",
375			 "port-irq14",
376			 "port-irq15";
377	port-irq0-pins = <6>;
378	port-irq11-pins = <0>;
379	port-irq12-pins = <1>;
380	port-irq14-pins = <4>;
381	port-irq15-pins = <8>;
382};
383
384&ioport9 {
385	port-irqs = <&port_irq8 &port_irq9 &port_irq10
386	&port_irq11>;
387	port-irq-names = "port-irq8",
388			 "port-irq9",
389			 "port-irq10",
390			 "port-irq11";
391	port-irq8-pins = <5>;
392	port-irq9-pins = <6>;
393	port-irq10-pins = <7>;
394	port-irq11-pins = <8>;
395};
396
397&ioporta {
398	port-irqs = <&port_irq4 &port_irq5 &port_irq6>;
399	port-irq-names = "port-irq4",
400			 "port-irq5",
401			 "port-irq6";
402	port-irq4-pins = <10>;
403	port-irq5-pins = <9>;
404	port-irq6-pins = <8>;
405};
406