1# Copyright (c) 2023, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32F4 PLL I2S node binding:
6
7  Takes same input as Main PLL. PLLM factor and PLL source are common with Main PLL
8
9  1 output clocks supported, the frequency can be computed with the following formula:
10
11    f(PLL_R) = f(VCO clock) / PLLR  --> PLLI2S
12
13      with f(VCO clock) = f(PLL clock input) × (PLLNI2S / PLLM)
14
15
16compatible: "st,stm32f4-plli2s-clock"
17
18include: [clock-controller.yaml, base.yaml]
19
20properties:
21  "#clock-cells":
22    const: 0
23
24  mul-n:
25    type: int
26    required: true
27    description: |
28        PLLI2S multiplication factor for VCO
29        Valid range may vary between parts: 50 - 432 , 192 - 432
30
31  div-r:
32    type: int
33    required: true
34    description: |
35        PLLI2S division factor for I2S Clocks
36    enum:
37      - 2
38      - 3
39      - 4
40      - 5
41      - 6
42      - 7
43