Lines Matching +full:pll +full:- +full:clock +full:- +full:cells

2 # SPDX-License-Identifier: Apache-2.0
5   Main PLL node binding for Connectivity line devices (STM32F105/STM32F107)
7   Takes one of clk_hse, pll2 or clk_hsi as input clock.
8   When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
11   Output clock frequency can be computed with the following formula:
13     f(PLLCLK) = f(PLLIN) x PLLMUL         --> SYSCLK (System Clock)
19   The PLL output frequency must not exceed 72 MHz.
22 compatible: "st,stm32f105-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27   "#clock-cells":
37         Main PLL multiplication factor for VCO.
40       - 4   # x4
41       - 5   # x5
42       - 6   # x6
43       - 7   # x7
44       - 8   # x8
45       - 9   # x9
46       - 15  # x6.5
53         Valid range: 1 - 16
58         Optional PLL output divisor to generate a 48MHz USB clock.
59         When set, PLL output clock is not divided.
60         Otherwise, PLL output clock is divided by 1.5.