Lines Matching +full:pll +full:- +full:clock +full:- +full:cells
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/ra_clock.h>
8 #include <arm/renesas/ra/ra4/ra4-cm4-common.dtsi>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &adc1;
16 compatible = "mmio-sram";
20 flash-controller@407e0000 {
22 compatible = "soc-nv-flash";
28 compatible = "renesas,ra-sci";
30 interrupt-names = "rxi", "txi", "tei", "eri";
35 compatible = "renesas,ra-sci-uart";
42 compatible = "renesas,ra-spi";
44 interrupt-names = "rxi", "txi", "tei", "eri";
48 compatible = "renesas,ra-sce5-rng";
54 channel-count = <8>;
55 channel-available-mask = <0x1a0670>;
59 compatible = "renesas,ra-pwm";
64 #pwm-cells = <3>;
70 #address-cells = <1>;
71 #size-cells = <1>;
73 xtal: clock-main-osc {
74 compatible = "renesas,ra-cgc-external-clock";
75 clock-frequency = <DT_FREQ_M(8)>;
76 #clock-cells = <0>;
80 hoco: clock-hoco {
81 compatible = "fixed-clock";
82 clock-frequency = <DT_FREQ_M(48)>;
83 #clock-cells = <0>;
86 moco: clock-moco {
87 compatible = "fixed-clock";
88 clock-frequency = <DT_FREQ_M(8)>;
89 #clock-cells = <0>;
92 loco: clock-loco {
93 compatible = "fixed-clock";
94 clock-frequency = <32768>;
95 #clock-cells = <0>;
98 subclk: clock-subclk {
99 compatible = "renesas,ra-cgc-subclk";
100 clock-frequency = <32768>;
101 #clock-cells = <0>;
105 pll: pll { label
106 compatible = "renesas,ra-cgc-pll";
107 #clock-cells = <0>;
109 /* PLL */
117 compatible = "renesas,ra-cgc-pclk-block";
120 reg-names = "MSTPA", "MSTPB","MSTPC",
122 #clock-cells = <0>;
127 compatible = "renesas,ra-cgc-pclk";
129 #clock-cells = <2>;
134 compatible = "renesas,ra-cgc-pclk";
136 #clock-cells = <2>;
141 compatible = "renesas,ra-cgc-pclk";
143 #clock-cells = <2>;
148 compatible = "renesas,ra-cgc-pclk";
150 #clock-cells = <2>;
155 compatible = "renesas,ra-cgc-pclk";
157 #clock-cells = <2>;
162 compatible = "renesas,ra-cgc-pclk";
164 #clock-cells = <2>;
169 compatible = "renesas,ra-cgc-pclk";
170 #clock-cells = <2>;
175 compatible = "renesas,ra-cgc-pclk";
177 #clock-cells = <2>;
185 port-irqs = <&port_irq3 &port_irq7 &port_irq14
187 port-irq-names = "port-irq3",
188 "port-irq7",
189 "port-irq14",
190 "port-irq15";
191 port-irq3-pins = <4>;
192 port-irq7-pins = <15>;
193 port-irq14-pins = <10>;
194 port-irq15-pins = <11>;
198 port-irqs = <&port_irq0 &port_irq1 &port_irq2
200 port-irq-names = "port-irq0",
201 "port-irq1",
202 "port-irq2",
203 "port-irq3",
204 "port-irq4";
205 port-irq0-pins = <5>;
206 port-irq1-pins = <1 4>;
207 port-irq2-pins = <0>;
208 port-irq3-pins = <10>;
209 port-irq4-pins = <11>;
213 port-irqs = <&port_irq0 &port_irq1 &port_irq2
215 port-irq-names = "port-irq0",
216 "port-irq1",
217 "port-irq2",
218 "port-irq3";
219 port-irq0-pins = <6>;
220 port-irq1-pins = <5>;
221 port-irq2-pins = <13>;
222 port-irq3-pins = <12>;
226 port-irqs = <&port_irq4 &port_irq6 &port_irq9>;
227 port-irq-names = "port-irq4",
228 "port-irq6",
229 "port-irq9";
230 port-irq4-pins = <2>;
231 port-irq6-pins = <9>;
232 port-irq9-pins = <14>;
236 port-irqs = <&port_irq11>;
237 port-irq-names = "port-irq11";
238 port-irq11-pins = <1>;