1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/clock/ra_clock.h>
8#include <arm/renesas/ra/ra4/ra4-cm4-common.dtsi>
9#include <zephyr/dt-bindings/pwm/ra_pwm.h>
10
11/delete-node/ &adc1;
12
13/ {
14	soc {
15		sram0: memory@20000000 {
16			compatible = "mmio-sram";
17			reg = <0x20000000 DT_SIZE_K(96)>;
18		};
19
20		flash-controller@407e0000 {
21			flash0: flash@0 {
22				compatible = "soc-nv-flash";
23				reg = <0x0 DT_SIZE_K(512)>;
24			};
25		};
26
27		sci4: sci4@40070080  {
28			compatible = "renesas,ra-sci";
29			interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
30			interrupt-names = "rxi", "txi", "tei", "eri";
31			reg = <0x40070080 0x20>;
32			clocks = <&pclka MSTPB 26>;
33			status = "disabled";
34			uart {
35				compatible = "renesas,ra-sci-uart";
36				channel = <4>;
37				status = "disabled";
38			};
39		};
40
41		spi1: spi@40072100 {
42			compatible = "renesas,ra-spi";
43			interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
44			interrupt-names = "rxi", "txi", "tei", "eri";
45		};
46
47		trng: trng {
48			compatible = "renesas,ra-sce5-rng";
49			status = "disabled";
50		};
51
52		adc@4005c000 {
53			interrupts = <20 1>;
54			channel-count = <8>;
55			channel-available-mask = <0x1a0670>;
56		};
57
58		pwm8: pwm8@40169800 {
59			compatible = "renesas,ra-pwm";
60			divider = <RA_PWM_SOURCE_DIV_1>;
61			channel = <RA_PWM_CHANNEL_8>;
62			clocks = <&pclkd MSTPD 6>;
63			reg = <0x40169800 0x100>;
64			#pwm-cells = <3>;
65			status = "disabled";
66		};
67	};
68
69	clocks: clocks {
70		#address-cells = <1>;
71		#size-cells = <1>;
72
73		xtal: clock-main-osc {
74			compatible = "renesas,ra-cgc-external-clock";
75			clock-frequency = <DT_FREQ_M(8)>;
76			#clock-cells = <0>;
77			status = "disabled";
78		};
79
80		hoco: clock-hoco {
81			compatible = "fixed-clock";
82			clock-frequency = <DT_FREQ_M(48)>;
83			#clock-cells = <0>;
84		};
85
86		moco: clock-moco {
87			compatible = "fixed-clock";
88			clock-frequency = <DT_FREQ_M(8)>;
89			#clock-cells = <0>;
90		};
91
92		loco: clock-loco {
93			compatible = "fixed-clock";
94			clock-frequency = <32768>;
95			#clock-cells = <0>;
96		};
97
98		subclk: clock-subclk {
99			compatible = "renesas,ra-cgc-subclk";
100			clock-frequency = <32768>;
101			#clock-cells = <0>;
102			status = "disabled";
103		};
104
105		pll: pll {
106			compatible = "renesas,ra-cgc-pll";
107			#clock-cells = <0>;
108
109			/* PLL */
110			clocks = <&xtal>;
111			div = <2>;
112			mul = <12 0>;
113			status = "disabled";
114		};
115
116		pclkblock: pclkblock@4001e01c {
117			compatible = "renesas,ra-cgc-pclk-block";
118			reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
119			      <0x40047008 4>;
120			reg-names = "MSTPA", "MSTPB","MSTPC",
121				    "MSTPD";
122			#clock-cells = <0>;
123			clocks = <&hoco>;
124			status = "okay";
125
126			iclk: iclk {
127				compatible = "renesas,ra-cgc-pclk";
128				div = <1>;
129				#clock-cells = <2>;
130				status = "okay";
131			};
132
133			pclka: pclka {
134				compatible = "renesas,ra-cgc-pclk";
135				div = <1>;
136				#clock-cells = <2>;
137				status = "okay";
138			};
139
140			pclkb: pclkb {
141				compatible = "renesas,ra-cgc-pclk";
142				div = <2>;
143				#clock-cells = <2>;
144				status = "okay";
145			};
146
147			pclkc: pclkc {
148				compatible = "renesas,ra-cgc-pclk";
149				div = <1>;
150				#clock-cells = <2>;
151				status = "okay";
152			};
153
154			pclkd: pclkd {
155				compatible = "renesas,ra-cgc-pclk";
156				div = <1>;
157				#clock-cells = <2>;
158				status = "okay";
159			};
160
161			fclk: fclk {
162				compatible = "renesas,ra-cgc-pclk";
163				div = <2>;
164				#clock-cells = <2>;
165				status = "okay";
166			};
167
168			clkout: clkout {
169				compatible = "renesas,ra-cgc-pclk";
170				#clock-cells = <2>;
171				status = "disabled";
172			};
173
174			uclk: uclk {
175				compatible = "renesas,ra-cgc-pclk";
176				div = <1>;
177				#clock-cells = <2>;
178				status = "okay";
179			};
180		};
181	};
182};
183
184&ioport0 {
185	port-irqs = <&port_irq3 &port_irq7 &port_irq14
186	&port_irq15>;
187	port-irq-names = "port-irq3",
188			 "port-irq7",
189			 "port-irq14",
190			 "port-irq15";
191	port-irq3-pins = <4>;
192	port-irq7-pins = <15>;
193	port-irq14-pins = <10>;
194	port-irq15-pins = <11>;
195};
196
197&ioport1 {
198	port-irqs = <&port_irq0 &port_irq1 &port_irq2
199	&port_irq3 &port_irq4>;
200	port-irq-names = "port-irq0",
201			 "port-irq1",
202			 "port-irq2",
203			 "port-irq3",
204			 "port-irq4";
205	port-irq0-pins = <5>;
206	port-irq1-pins = <1 4>;
207	port-irq2-pins = <0>;
208	port-irq3-pins = <10>;
209	port-irq4-pins = <11>;
210};
211
212&ioport2 {
213	port-irqs = <&port_irq0 &port_irq1 &port_irq2
214	&port_irq3>;
215	port-irq-names = "port-irq0",
216			 "port-irq1",
217			 "port-irq2",
218			 "port-irq3";
219	port-irq0-pins = <6>;
220	port-irq1-pins = <5>;
221	port-irq2-pins = <13>;
222	port-irq3-pins = <12>;
223};
224
225&ioport4 {
226	port-irqs = <&port_irq4 &port_irq6 &port_irq9>;
227	port-irq-names = "port-irq4",
228			 "port-irq6",
229			 "port-irq9";
230	port-irq4-pins = <2>;
231	port-irq6-pins = <9>;
232	port-irq9-pins = <14>;
233};
234
235&ioport5 {
236	port-irqs = <&port_irq11>;
237	port-irq-names = "port-irq11";
238	port-irq11-pins = <1>;
239};
240