1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32F2 Main PLL node binding:
6
7  Takes one of clk_hse or clk_hsi as input clock.
8
9  Up to 2 output clocks could be supported and for each output clock, the
10  frequency can be computed with the following formula:
11
12    f(PLL_P) = f(VCO clock) / PLLP  --> PLLCLK (System Clock)
13    f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48CLK (Optional)
14
15      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
16
17  The PLL output frequency must not exceed 168 MHz.
18
19
20compatible: "st,stm32f2-pll-clock"
21
22include: [clock-controller.yaml, base.yaml]
23
24properties:
25  "#clock-cells":
26    const: 0
27
28  clocks:
29    required: true
30
31  div-m:
32    type: int
33    required: true
34    description: |
35        Division factor for the PLL input clock
36        Valid range: 2 - 63
37
38  mul-n:
39    type: int
40    required: true
41    description: |
42        PLL multiplication factor for VCO
43        Valid range: 192 - 432
44
45  div-p:
46    type: int
47    required: true
48    description: |
49        PLL division factor for PLLCLK
50    enum:
51      - 2
52      - 4
53      - 6
54      - 8
55
56  div-q:
57    type: int
58    description: |
59        PLL division factor for PLL48CK
60        Valid range: 2 - 15
61