1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
8#include <zephyr/dt-bindings/clock/ra_clock.h>
9#include <zephyr/dt-bindings/pwm/ra_pwm.h>
10
11/delete-node/ &spi1;
12
13/ {
14	soc {
15		sram0: memory@20000000 {
16			compatible = "mmio-sram";
17			reg = <0x20000000 DT_SIZE_K(128)>;
18		};
19
20		ioport6: gpio@400800c0 {
21			compatible = "renesas,ra-gpio-ioport";
22			reg = <0x400800c0 0x20>;
23			port = <6>;
24			gpio-controller;
25			#gpio-cells = <2>;
26			ngpios = <16>;
27			status = "disabled";
28		};
29
30		ioport7: gpio@400800e0 {
31			compatible = "renesas,ra-gpio-ioport";
32			reg = <0x400800e0 0x20>;
33			port = <7>;
34			gpio-controller;
35			#gpio-cells = <2>;
36			ngpios = <16>;
37			status = "disabled";
38		};
39
40		ioport8: gpio@40080100 {
41			compatible = "renesas,ra-gpio-ioport";
42			reg = <0x40080100 0x20>;
43			port = <8>;
44			gpio-controller;
45			#gpio-cells = <2>;
46			ngpios = <16>;
47			status = "disabled";
48		};
49
50		sci1: sci1@40118100 {
51			compatible = "renesas,ra-sci";
52			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
53			interrupt-names = "rxi", "txi", "tei", "eri";
54			reg = <0x40118100 0x100>;
55			clocks = <&pclka MSTPB 30>;
56			status = "disabled";
57			uart {
58				compatible = "renesas,ra-sci-uart";
59				channel = <1>;
60				status = "disabled";
61			};
62		};
63
64		sci2: sci2@40118200 {
65			compatible = "renesas,ra-sci";
66			interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
67			interrupt-names = "rxi", "txi", "tei", "eri";
68			reg = <0x40118200 0x100>;
69			clocks = <&pclka MSTPB 29>;
70			status = "disabled";
71			uart {
72				compatible = "renesas,ra-sci-uart";
73				channel = <2>;
74				status = "disabled";
75			};
76		};
77
78		sci3: sci3@40118300 {
79			compatible = "renesas,ra-sci";
80			interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
81			interrupt-names = "rxi", "txi", "tei", "eri";
82			reg = <0x40118300 0x100>;
83			clocks = <&pclka MSTPB 28>;
84			status = "disabled";
85			uart {
86				compatible = "renesas,ra-sci-uart";
87				channel = <3>;
88				status = "disabled";
89			};
90		};
91
92		sci4: sci4@40118400 {
93			compatible = "renesas,ra-sci";
94			interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
95			interrupt-names = "rxi", "txi", "tei", "eri";
96			reg = <0x40118400 0x100>;
97			clocks = <&pclka MSTPB 27>;
98			status = "disabled";
99			uart {
100				compatible = "renesas,ra-sci-uart";
101				channel = <4>;
102				status = "disabled";
103			};
104		};
105
106		adc@40170000 {
107			channel-count = <12>;
108			channel-available-mask = <0x33ff>;
109		};
110
111		adc@40170200 {
112			channel-count = <10>;
113			channel-available-mask = <0x7f0007>;
114		};
115
116		pwm2: pwm2@40169200 {
117			compatible = "renesas,ra-pwm";
118			divider = <RA_PWM_SOURCE_DIV_1>;
119			channel = <RA_PWM_CHANNEL_2>;
120			clocks = <&pclkd MSTPE 29>;
121			reg = <0x40169200 0x100>;
122			#pwm-cells = <3>;
123			status = "disabled";
124		};
125
126		pwm3: pwm3@40169300 {
127			compatible = "renesas,ra-pwm";
128			divider = <RA_PWM_SOURCE_DIV_1>;
129			channel = <RA_PWM_CHANNEL_3>;
130			clocks = <&pclkd MSTPE 28>;
131			reg = <0x40169300 0x100>;
132			#pwm-cells = <3>;
133			status = "disabled";
134		};
135
136		pwm6: pwm6@40169600 {
137			compatible = "renesas,ra-pwm";
138			divider = <RA_PWM_SOURCE_DIV_1>;
139			channel = <RA_PWM_CHANNEL_6>;
140			clocks = <&pclkd MSTPE 25>;
141			reg = <0x40169600 0x100>;
142			#pwm-cells = <3>;
143			status = "disabled";
144		};
145
146		pwm7: pwm7@40169700 {
147			compatible = "renesas,ra-pwm";
148			divider = <RA_PWM_SOURCE_DIV_1>;
149			channel = <RA_PWM_CHANNEL_7>;
150			clocks = <&pclkd MSTPE 24>;
151			reg = <0x40169700 0x100>;
152			#pwm-cells = <3>;
153			status = "disabled";
154		};
155	};
156
157	clocks: clocks {
158		#address-cells = <1>;
159		#size-cells = <1>;
160
161		xtal: clock-main-osc {
162			compatible = "renesas,ra-cgc-external-clock";
163			clock-frequency = <DT_FREQ_M(24)>;
164			#clock-cells = <0>;
165			status = "disabled";
166		};
167
168		hoco: clock-hoco {
169			compatible = "fixed-clock";
170			clock-frequency = <DT_FREQ_M(20)>;
171			#clock-cells = <0>;
172		};
173
174		moco: clock-moco {
175			compatible = "fixed-clock";
176			clock-frequency = <DT_FREQ_M(8)>;
177			#clock-cells = <0>;
178		};
179
180		loco: clock-loco {
181			compatible = "fixed-clock";
182			clock-frequency = <32768>;
183			#clock-cells = <0>;
184		};
185
186		subclk: clock-subclk {
187			compatible = "renesas,ra-cgc-subclk";
188			clock-frequency = <32768>;
189			#clock-cells = <0>;
190			status = "disabled";
191		};
192
193		pll: pll {
194			compatible = "renesas,ra-cgc-pll";
195			#clock-cells = <0>;
196
197			/* PLL */
198			clocks = <&xtal>;
199			div = <3>;
200			mul = <25 0>;
201			status = "disabled";
202		};
203
204		pll2: pll2 {
205			compatible = "renesas,ra-cgc-pll";
206			#clock-cells = <0>;
207			div = <2>;
208			mul = <20 0>;
209			status = "disabled";
210		};
211
212		pclkblock: pclkblock@40084000 {
213			compatible = "renesas,ra-cgc-pclk-block";
214			reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
215			      <0x4008400c 4>, <0x40084010 4>;
216			reg-names = "MSTPA", "MSTPB","MSTPC",
217				    "MSTPD", "MSTPE";
218			#clock-cells = <0>;
219			clocks = <&pll>;
220			status = "okay";
221
222			iclk: iclk {
223				compatible = "renesas,ra-cgc-pclk";
224				div = <2>;
225				#clock-cells = <2>;
226				status = "okay";
227			};
228
229			pclka: pclka {
230				compatible = "renesas,ra-cgc-pclk";
231				div = <2>;
232				#clock-cells = <2>;
233				status = "okay";
234			};
235
236			pclkb: pclkb {
237				compatible = "renesas,ra-cgc-pclk";
238				div = <4>;
239				#clock-cells = <2>;
240				status = "okay";
241			};
242
243			pclkc: pclkc {
244				compatible = "renesas,ra-cgc-pclk";
245				div = <4>;
246				#clock-cells = <2>;
247				status = "okay";
248			};
249
250			pclkd: pclkd {
251				compatible = "renesas,ra-cgc-pclk";
252				div = <2>;
253				#clock-cells = <2>;
254				status = "okay";
255			};
256
257			fclk: fclk {
258				compatible = "renesas,ra-cgc-pclk";
259				div = <4>;
260				#clock-cells = <2>;
261				status = "okay";
262			};
263
264			clkout: clkout {
265				compatible = "renesas,ra-cgc-pclk";
266				#clock-cells = <2>;
267				status = "disabled";
268			};
269
270			uclk: uclk {
271				compatible = "renesas,ra-cgc-pclk";
272				#clock-cells = <2>;
273				status = "disabled";
274			};
275		};
276	};
277};
278
279&ioport0 {
280	port-irqs = <&port_irq6 &port_irq7 &port_irq8
281	&port_irq9 &port_irq10 &port_irq11
282	&port_irq12 &port_irq13>;
283	port-irq-names = "port-irq6",
284			 "port-irq7",
285			 "port-irq8",
286			 "port-irq9",
287			 "port-irq10",
288			 "port-irq11",
289			 "port-irq12",
290			 "port-irq13";
291	port-irq6-pins = <0>;
292	port-irq7-pins = <1>;
293	port-irq8-pins = <2>;
294	port-irq9-pins = <4>;
295	port-irq10-pins = <5>;
296	port-irq11-pins = <6>;
297	port-irq12-pins = <8>;
298	port-irq13-pins = <9 15>;
299};
300
301&ioport1 {
302	port-irqs = <&port_irq0 &port_irq1 &port_irq2
303	&port_irq3 &port_irq4>;
304	port-irq-names = "port-irq0",
305			 "port-irq1",
306			 "port-irq2",
307			 "port-irq3",
308			 "port-irq4";
309	port-irq0-pins = <5>;
310	port-irq1-pins = <1 4>;
311	port-irq2-pins = <0>;
312	port-irq3-pins = <10>;
313	port-irq4-pins = <11>;
314};
315
316&ioport2 {
317	port-irqs = <&port_irq0 &port_irq1 &port_irq2
318	&port_irq3>;
319	port-irq-names = "port-irq0",
320			 "port-irq1",
321			 "port-irq2",
322			 "port-irq3";
323	port-irq0-pins = <6>;
324	port-irq1-pins = <5>;
325	port-irq2-pins = <3 13>;
326	port-irq3-pins = <2 12>;
327};
328
329&ioport3 {
330	port-irqs = <&port_irq5 &port_irq6
331	&port_irq8 &port_irq9>;
332	port-irq-names = "port-irq5",
333			 "port-irq6",
334			 "port-irq8",
335			 "port-irq9";
336	port-irq5-pins = <2>;
337	port-irq6-pins = <1>;
338	port-irq8-pins = <5>;
339	port-irq9-pins = <4>;
340};
341
342&ioport4 {
343	port-irqs = <&port_irq0 &port_irq4 &port_irq5
344	&port_irq6 &port_irq7 &port_irq8
345	&port_irq9 &port_irq14 &port_irq15>;
346	port-irq-names = "port-irq0",
347			 "port-irq4",
348			 "port-irq5",
349			 "port-irq6",
350			 "port-irq7",
351			 "port-irq8",
352			 "port-irq9",
353			 "port-irq14",
354			 "port-irq15";
355	port-irq0-pins = <0>;
356	port-irq4-pins = <2 11>;
357	port-irq5-pins = <1 10>;
358	port-irq6-pins = <9>;
359	port-irq7-pins = <8>;
360	port-irq8-pins = <15>;
361	port-irq9-pins = <14>;
362	port-irq14-pins = <3>;
363	port-irq15-pins = <4>;
364};
365
366&ioport5 {
367	port-irqs = <&port_irq11 &port_irq12 &port_irq14
368	&port_irq15>;
369	port-irq-names = "port-irq11",
370			 "port-irq12",
371			 "port-irq14",
372			 "port-irq15";
373	port-irq11-pins = <1>;
374	port-irq12-pins = <2>;
375	port-irq14-pins = <5 12>;
376	port-irq15-pins = <6 11>;
377};
378
379&ioport7 {
380	port-irqs = <&port_irq10 &port_irq11>;
381	port-irq-names = "port-irq10",
382			 "port-irq11";
383	port-irq10-pins = <9>;
384	port-irq11-pins = <8>;
385};
386