Lines Matching +full:pll +full:- +full:clock +full:- +full:cells

2 # SPDX-License-Identifier: Apache-2.0
5   STM32F4 PLL I2S node binding:
7   Takes same input as Main PLL. PLLM factor and PLL source are common with Main PLL
11     f(PLL_R) = f(VCO clock) / PLLR  --> PLLI2S
13       with f(VCO clock) = f(PLL clock input) × (PLLNI2S / PLLM)
16 compatible: "st,stm32f4-plli2s-clock"
18 include: [clock-controller.yaml, base.yaml]
21   "#clock-cells":
24   mul-n:
29         Valid range may vary between parts: 50 - 432 , 192 - 432
31   div-r:
37       - 2
38       - 3
39       - 4
40       - 5
41       - 6
42       - 7