1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32F7 Main PLL node binding:
6
7  Takes one of clk_hse or clk_hsi as input clock.
8
9  Up to 2 output clocks could be supported and for each output clock, the
10  frequency can be computed with the following formula:
11
12    f(PLL_P) = f(VCO clock) / PLLP  --> PLLCLK (System Clock)
13    f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48CLK (Optional)
14
15      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
16
17
18compatible: "st,stm32f7-pll-clock"
19
20include: [clock-controller.yaml, base.yaml]
21
22properties:
23  "#clock-cells":
24    const: 0
25
26  clocks:
27    required: true
28
29  div-m:
30    type: int
31    required: true
32    description: |
33        Division factor for the PLL input clock
34        Valid range: 2 - 63
35
36  mul-n:
37    type: int
38    required: true
39    description: |
40        PLL multiplication factor for VCO
41        Valid range: 50 - 432
42
43  div-p:
44    type: int
45    required: true
46    description: |
47        PLL division factor for PLLCLK
48    enum:
49      - 2
50      - 4
51      - 6
52      - 8
53
54  div-q:
55    type: int
56    description: |
57        PLL division factor for PLL48CK
58        Valid range: 2 - 15
59