1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/renesas/ra/ra8/ra8x1.dtsi>
8#include <zephyr/dt-bindings/clock/ra_clock.h>
9
10/ {
11	soc {
12		sdram: sdram-controller@40002000 {
13			compatible = "renesas,ra-sdram";
14			#address-cells = <1>;
15			#size-cells = <0>;
16			reg = <0x40002000 0xFFF>;
17			status = "disabled";
18		};
19
20		lcdif: display-controller@40342000 {
21			compatible = "renesas,ra-glcdc";
22			reg = <0x40342000 0x1454>;
23			clocks = <&lcdclk MSTPC 4>;
24			interrupts = <71 1>;
25			interrupt-names = "line";
26			status = "disabled";
27		};
28
29		mipi_dsi: dsihost@40346000 {
30			compatible = "renesas,ra-mipi-dsi";
31			#address-cells = <1>;
32			#size-cells = <0>;
33			reg = <0x40346000 0x2000>;
34			interrupts = <72 12>, <73 12>, <74 12>, <75 12>, <76 12>, <77 12>;
35			interrupt-names = "sq0", "sq1", "vm", "rcv", "ferr", "ppi";
36			clocks = <&lcdclk MSTPC 10>;
37			status = "disabled";
38		};
39	};
40
41	clocks: clocks {
42		#address-cells = <1>;
43		#size-cells = <1>;
44
45		xtal: clock-main-osc {
46			compatible = "renesas,ra-cgc-external-clock";
47			clock-frequency = <DT_FREQ_M(20)>;
48			#clock-cells = <0>;
49			status = "disabled";
50		};
51
52		hoco: clock-hoco {
53			compatible = "fixed-clock";
54			clock-frequency = <DT_FREQ_M(48)>;
55			#clock-cells = <0>;
56		};
57
58		moco: clock-moco {
59			compatible = "fixed-clock";
60			clock-frequency = <DT_FREQ_M(8)>;
61			#clock-cells = <0>;
62		};
63
64		loco: clock-loco {
65			compatible = "fixed-clock";
66			clock-frequency = <32768>;
67			#clock-cells = <0>;
68		};
69
70		subclk: clock-subclk {
71			compatible = "renesas,ra-cgc-subclk";
72			clock-frequency = <32768>;
73			#clock-cells = <0>;
74			status = "disabled";
75		};
76
77		pll: pll {
78			compatible = "renesas,ra-cgc-pll";
79			#clock-cells = <0>;
80
81			/* PLL */
82			clocks = <&xtal>;
83			div = <2>;
84			mul = <96 0>;
85
86			pllp: pllp {
87				compatible = "renesas,ra-cgc-pll-out";
88				div = <2>;
89				freq = <DT_FREQ_M(480)>;
90				status = "disabled";
91				#clock-cells = <0>;
92			};
93
94			pllq: pllq {
95				compatible = "renesas,ra-cgc-pll-out";
96				div = <2>;
97				freq = <DT_FREQ_M(480)>;
98				status = "disabled";
99				#clock-cells = <0>;
100			};
101
102			pllr: pllr {
103				compatible = "renesas,ra-cgc-pll-out";
104				div = <2>;
105				freq = <DT_FREQ_M(480)>;
106				status = "disabled";
107				#clock-cells = <0>;
108			};
109			status = "disabled";
110		};
111
112		pll2: pll2 {
113			compatible = "renesas,ra-cgc-pll";
114			#clock-cells = <0>;
115
116			/* PLL2 */
117			div = <2>;
118			mul = <96 0>;
119
120			pll2p: pll2p {
121				compatible = "renesas,ra-cgc-pll-out";
122				div = <2>;
123				freq = <DT_FREQ_M(0)>;
124				status = "disabled";
125				#clock-cells = <0>;
126			};
127
128			pll2q: pll2q {
129				compatible = "renesas,ra-cgc-pll-out";
130				div = <2>;
131				freq = <DT_FREQ_M(0)>;
132				status = "disabled";
133				#clock-cells = <0>;
134			};
135
136			pll2r: pll2r {
137				compatible = "renesas,ra-cgc-pll-out";
138				div = <2>;
139				freq = <DT_FREQ_M(0)>;
140				status = "disabled";
141				#clock-cells = <0>;
142			};
143			status = "disabled";
144		};
145
146		pclkblock: pclkblock@40203000 {
147			compatible = "renesas,ra-cgc-pclk-block";
148			reg = <0x40203000 4>, <0x40203004 4>, <0x40203008 4>,
149			      <0x4020300c 4>, <0x40203010 4>;
150			reg-names = "MSTPA", "MSTPB","MSTPC",
151				    "MSTPD", "MSTPE";
152			#clock-cells = <0>;
153			clocks = <&pllp>;
154			status = "okay";
155
156			cpuclk: cpuclk {
157				compatible = "renesas,ra-cgc-pclk";
158				div = <1>;
159				#clock-cells = <2>;
160				status = "okay";
161			};
162
163			iclk: iclk {
164				compatible = "renesas,ra-cgc-pclk";
165				div = <2>;
166				#clock-cells = <2>;
167				status = "okay";
168			};
169
170			pclka: pclka {
171				compatible = "renesas,ra-cgc-pclk";
172				div = <4>;
173				#clock-cells = <2>;
174				status = "okay";
175			};
176
177			pclkb: pclkb {
178				compatible = "renesas,ra-cgc-pclk";
179				div = <8>;
180				#clock-cells = <2>;
181				status = "okay";
182			};
183
184			pclkc: pclkc {
185				compatible = "renesas,ra-cgc-pclk";
186				div = <8>;
187				#clock-cells = <2>;
188				status = "okay";
189			};
190
191			pclkd: pclkd {
192				compatible = "renesas,ra-cgc-pclk";
193				div = <4>;
194				#clock-cells = <2>;
195				status = "okay";
196			};
197
198			pclke: pclke {
199				compatible = "renesas,ra-cgc-pclk";
200				div = <2>;
201				#clock-cells = <2>;
202				status = "okay";
203			};
204
205			bclk: bclk {
206				compatible = "renesas,ra-cgc-pclk";
207				div = <4>;
208				bclkout: bclkout {
209					compatible = "renesas,ra-cgc-busclk";
210					clk-out-div = <2>;
211					sdclk = <1>;
212					#clock-cells = <0>;
213				};
214				#clock-cells = <2>;
215				status = "okay";
216			};
217
218			fclk: fclk {
219				compatible = "renesas,ra-cgc-pclk";
220				div = <8>;
221				#clock-cells = <2>;
222				status = "okay";
223			};
224
225			clkout: clkout {
226				compatible = "renesas,ra-cgc-pclk";
227				#clock-cells = <2>;
228				status = "disabled";
229			};
230
231			sciclk: sciclk {
232				compatible = "renesas,ra-cgc-pclk";
233				#clock-cells = <2>;
234				status = "disabled";
235			};
236
237			spiclk: spiclk {
238				compatible = "renesas,ra-cgc-pclk";
239				#clock-cells = <2>;
240				status = "disabled";
241			};
242
243			canfdclk: canfdclk {
244				compatible = "renesas,ra-cgc-pclk";
245				#clock-cells = <2>;
246				status = "disabled";
247			};
248
249			i3cclk: i3cclk {
250				compatible = "renesas,ra-cgc-pclk";
251				#clock-cells = <2>;
252				status = "disabled";
253			};
254
255			uclk: uclk {
256				compatible = "renesas,ra-cgc-pclk";
257				#clock-cells = <2>;
258				status = "disabled";
259			};
260
261			u60clk: u60clk {
262				compatible = "renesas,ra-cgc-pclk";
263				#clock-cells = <2>;
264				status = "disabled";
265			};
266
267			octaspiclk: octaspiclk {
268				compatible = "renesas,ra-cgc-pclk";
269				#clock-cells = <2>;
270				status = "disabled";
271			};
272
273			lcdclk: lcdclk {
274				compatible = "renesas,ra-cgc-pclk";
275				#clock-cells = <2>;
276				status = "disabled";
277			};
278		};
279	};
280
281	soc {
282		usbhs: usbhs@40351000 {
283			compatible = "renesas,ra-usb";
284			reg = <0x40351000 0x2000>;
285			interrupts = <54 12>, <55 12>, <56 12>;
286			interrupt-names = "usbhs-ir", "usbhs-d0", "usbhs-d1";
287			num-bidir-endpoints = <10>;
288			phys = <&usbhs_phy>;
289			status = "disabled";
290			udc {
291				compatible = "renesas,ra-udc";
292				status = "disabled";
293			};
294		};
295	};
296
297	usbhs_phy: usbhs-phy {
298		compatible = "renesas,ra-usbphyc";
299		#phy-cells = <0>;
300	};
301};
302
303&ioport0 {
304	port-irqs = <&port_irq6 &port_irq7 &port_irq8
305	&port_irq9 &port_irq10 &port_irq11
306	&port_irq12 &port_irq13 &port_irq14>;
307	port-irq-names = "port-irq6",
308			 "port-irq7",
309			 "port-irq8",
310			 "port-irq9",
311			 "port-irq10",
312			 "port-irq11",
313			 "port-irq12",
314			 "port-irq13",
315			 "port-irq14";
316	port-irq6-pins = <0>;
317	port-irq7-pins = <1>;
318	port-irq8-pins = <2>;
319	port-irq9-pins = <4>;
320	port-irq10-pins = <5>;
321	port-irq11-pins = <6>;
322	port-irq12-pins = <8>;
323	port-irq13-pins = <9 15>;
324	port-irq14-pins = <10>;
325};
326
327&ioport1 {
328	port-irqs = <&port_irq0 &port_irq1 &port_irq2>;
329	port-irq-names = "port-irq0",
330			 "port-irq1",
331			 "port-irq2";
332	port-irq0-pins = <5>;
333	port-irq1-pins = <1 4>;
334	port-irq2-pins = <0>;
335};
336
337&ioport2 {
338	port-irqs = <&port_irq0 &port_irq1 &port_irq2
339	&port_irq3>;
340	port-irq-names = "port-irq0",
341			 "port-irq1",
342			 "port-irq2",
343			 "port-irq3";
344	port-irq0-pins = <6>;
345	port-irq1-pins = <5>;
346	port-irq2-pins = <3 13>;
347	port-irq3-pins = <2 8 12>;
348};
349
350&ioport3 {
351	port-irqs = <&port_irq4 &port_irq5 &port_irq6
352	&port_irq8 &port_irq9>;
353	port-irq-names = "port-irq4",
354			 "port-irq5",
355			 "port-irq6",
356			 "port-irq8",
357			 "port-irq9";
358	port-irq4-pins = <0>;
359	port-irq5-pins = <2>;
360	port-irq6-pins = <1>;
361	port-irq8-pins = <5>;
362	port-irq9-pins = <4>;
363};
364
365&ioport4 {
366	port-irqs = <&port_irq0 &port_irq4 &port_irq5
367	&port_irq6 &port_irq7 &port_irq8
368	&port_irq9 &port_irq14 &port_irq15>;
369	port-irq-names = "port-irq0",
370			 "port-irq4",
371			 "port-irq5",
372			 "port-irq6",
373			 "port-irq7",
374			 "port-irq8",
375			 "port-irq9",
376			 "port-irq14",
377			 "port-irq15";
378	port-irq0-pins = <0>;
379	port-irq4-pins = <2 11>;
380	port-irq5-pins = <1 10>;
381	port-irq6-pins = <9>;
382	port-irq7-pins = <8>;
383	port-irq8-pins = <15>;
384	port-irq9-pins = <14>;
385	port-irq14-pins = <3>;
386	port-irq15-pins = <4>;
387};
388
389&ioport5 {
390	port-irqs = <&port_irq1 &port_irq2 &port_irq3
391	&port_irq14 &port_irq15>;
392	port-irq-names = "port-irq1",
393			 "port-irq2",
394			 "port-irq3",
395			 "port-irq14",
396			 "port-irq15";
397	port-irq1-pins = <8>;
398	port-irq2-pins = <9>;
399	port-irq3-pins = <10>;
400	port-irq14-pins = <12>;
401	port-irq15-pins = <11>;
402};
403
404&ioport6 {
405	port-irqs = <&port_irq7>;
406	port-irq-names = "port-irq7";
407	port-irq7-pins = <15>;
408};
409
410&ioport7 {
411	port-irqs = <&port_irq7 &port_irq8 &port_irq10
412	&port_irq11>;
413	port-irq-names = "port-irq7",
414			 "port-irq8",
415			 "port-irq10",
416			 "port-irq11";
417	port-irq7-pins = <6>;
418	port-irq8-pins = <7>;
419	port-irq10-pins = <9>;
420	port-irq11-pins = <8>;
421};
422
423&ioport8 {
424	port-irqs = <&port_irq0 &port_irq11 &port_irq12
425	&port_irq14 &port_irq15>;
426	port-irq-names = "port-irq0",
427			 "port-irq11",
428			 "port-irq12",
429			 "port-irq14",
430			 "port-irq15";
431	port-irq0-pins = <6>;
432	port-irq11-pins = <0>;
433	port-irq12-pins = <1>;
434	port-irq14-pins = <4>;
435	port-irq15-pins = <8>;
436};
437
438&ioport9 {
439	port-irqs = <&port_irq8 &port_irq9 &port_irq10
440	&port_irq11>;
441	port-irq-names = "port-irq8",
442			 "port-irq9",
443			 "port-irq10",
444			 "port-irq11";
445	port-irq8-pins = <5>;
446	port-irq9-pins = <6>;
447	port-irq10-pins = <7>;
448	port-irq11-pins = <8>;
449};
450
451&ioporta {
452	port-irqs = <&port_irq4 &port_irq5 &port_irq6>;
453	port-irq-names = "port-irq4",
454			 "port-irq5",
455			 "port-irq6";
456	port-irq4-pins = <10>;
457	port-irq5-pins = <9>;
458	port-irq6-pins = <8>;
459};
460