/*
 * Copyright (c) 2024 Renesas Electronics Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <arm/renesas/ra/ra8/ra8x1.dtsi>
#include <zephyr/dt-bindings/clock/ra_clock.h>

/ {
	soc {
		sdram: sdram-controller@40002000 {
			compatible = "renesas,ra-sdram";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40002000 0xFFF>;
			status = "disabled";
		};

		lcdif: display-controller@40342000 {
			compatible = "renesas,ra-glcdc";
			reg = <0x40342000 0x1454>;
			clocks = <&lcdclk MSTPC 4>;
			interrupts = <71 1>;
			interrupt-names = "line";
			status = "disabled";
		};

		mipi_dsi: dsihost@40346000 {
			compatible = "renesas,ra-mipi-dsi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40346000 0x2000>;
			interrupts = <72 12>, <73 12>, <74 12>, <75 12>, <76 12>, <77 12>;
			interrupt-names = "sq0", "sq1", "vm", "rcv", "ferr", "ppi";
			clocks = <&lcdclk MSTPC 10>;
			status = "disabled";
		};
	};

	clocks: clocks {
		#address-cells = <1>;
		#size-cells = <1>;

		xtal: clock-main-osc {
			compatible = "renesas,ra-cgc-external-clock";
			clock-frequency = <DT_FREQ_M(20)>;
			#clock-cells = <0>;
			status = "disabled";
		};

		hoco: clock-hoco {
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_M(48)>;
			#clock-cells = <0>;
		};

		moco: clock-moco {
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_M(8)>;
			#clock-cells = <0>;
		};

		loco: clock-loco {
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			#clock-cells = <0>;
		};

		subclk: clock-subclk {
			compatible = "renesas,ra-cgc-subclk";
			clock-frequency = <32768>;
			#clock-cells = <0>;
			status = "disabled";
		};

		pll: pll {
			compatible = "renesas,ra-cgc-pll";
			#clock-cells = <0>;

			/* PLL */
			clocks = <&xtal>;
			div = <2>;
			mul = <96 0>;

			pllp: pllp {
				compatible = "renesas,ra-cgc-pll-out";
				div = <2>;
				freq = <DT_FREQ_M(480)>;
				status = "disabled";
				#clock-cells = <0>;
			};

			pllq: pllq {
				compatible = "renesas,ra-cgc-pll-out";
				div = <2>;
				freq = <DT_FREQ_M(480)>;
				status = "disabled";
				#clock-cells = <0>;
			};

			pllr: pllr {
				compatible = "renesas,ra-cgc-pll-out";
				div = <2>;
				freq = <DT_FREQ_M(480)>;
				status = "disabled";
				#clock-cells = <0>;
			};
			status = "disabled";
		};

		pll2: pll2 {
			compatible = "renesas,ra-cgc-pll";
			#clock-cells = <0>;

			/* PLL2 */
			div = <2>;
			mul = <96 0>;

			pll2p: pll2p {
				compatible = "renesas,ra-cgc-pll-out";
				div = <2>;
				freq = <DT_FREQ_M(0)>;
				status = "disabled";
				#clock-cells = <0>;
			};

			pll2q: pll2q {
				compatible = "renesas,ra-cgc-pll-out";
				div = <2>;
				freq = <DT_FREQ_M(0)>;
				status = "disabled";
				#clock-cells = <0>;
			};

			pll2r: pll2r {
				compatible = "renesas,ra-cgc-pll-out";
				div = <2>;
				freq = <DT_FREQ_M(0)>;
				status = "disabled";
				#clock-cells = <0>;
			};
			status = "disabled";
		};

		pclkblock: pclkblock@40203000 {
			compatible = "renesas,ra-cgc-pclk-block";
			reg = <0x40203000 4>, <0x40203004 4>, <0x40203008 4>,
			      <0x4020300c 4>, <0x40203010 4>;
			reg-names = "MSTPA", "MSTPB","MSTPC",
				    "MSTPD", "MSTPE";
			#clock-cells = <0>;
			clocks = <&pllp>;
			status = "okay";

			cpuclk: cpuclk {
				compatible = "renesas,ra-cgc-pclk";
				div = <1>;
				#clock-cells = <2>;
				status = "okay";
			};

			iclk: iclk {
				compatible = "renesas,ra-cgc-pclk";
				div = <2>;
				#clock-cells = <2>;
				status = "okay";
			};

			pclka: pclka {
				compatible = "renesas,ra-cgc-pclk";
				div = <4>;
				#clock-cells = <2>;
				status = "okay";
			};

			pclkb: pclkb {
				compatible = "renesas,ra-cgc-pclk";
				div = <8>;
				#clock-cells = <2>;
				status = "okay";
			};

			pclkc: pclkc {
				compatible = "renesas,ra-cgc-pclk";
				div = <8>;
				#clock-cells = <2>;
				status = "okay";
			};

			pclkd: pclkd {
				compatible = "renesas,ra-cgc-pclk";
				div = <4>;
				#clock-cells = <2>;
				status = "okay";
			};

			pclke: pclke {
				compatible = "renesas,ra-cgc-pclk";
				div = <2>;
				#clock-cells = <2>;
				status = "okay";
			};

			bclk: bclk {
				compatible = "renesas,ra-cgc-pclk";
				div = <4>;
				bclkout: bclkout {
					compatible = "renesas,ra-cgc-busclk";
					clk-out-div = <2>;
					sdclk = <1>;
					#clock-cells = <0>;
				};
				#clock-cells = <2>;
				status = "okay";
			};

			fclk: fclk {
				compatible = "renesas,ra-cgc-pclk";
				div = <8>;
				#clock-cells = <2>;
				status = "okay";
			};

			clkout: clkout {
				compatible = "renesas,ra-cgc-pclk";
				#clock-cells = <2>;
				status = "disabled";
			};

			sciclk: sciclk {
				compatible = "renesas,ra-cgc-pclk";
				#clock-cells = <2>;
				status = "disabled";
			};

			spiclk: spiclk {
				compatible = "renesas,ra-cgc-pclk";
				#clock-cells = <2>;
				status = "disabled";
			};

			canfdclk: canfdclk {
				compatible = "renesas,ra-cgc-pclk";
				#clock-cells = <2>;
				status = "disabled";
			};

			i3cclk: i3cclk {
				compatible = "renesas,ra-cgc-pclk";
				#clock-cells = <2>;
				status = "disabled";
			};

			uclk: uclk {
				compatible = "renesas,ra-cgc-pclk";
				#clock-cells = <2>;
				status = "disabled";
			};

			u60clk: u60clk {
				compatible = "renesas,ra-cgc-pclk";
				#clock-cells = <2>;
				status = "disabled";
			};

			octaspiclk: octaspiclk {
				compatible = "renesas,ra-cgc-pclk";
				#clock-cells = <2>;
				status = "disabled";
			};

			lcdclk: lcdclk {
				compatible = "renesas,ra-cgc-pclk";
				#clock-cells = <2>;
				status = "disabled";
			};
		};
	};

	soc {
		usbhs: usbhs@40351000 {
			compatible = "renesas,ra-usb";
			reg = <0x40351000 0x2000>;
			interrupts = <54 12>, <55 12>, <56 12>;
			interrupt-names = "usbhs-ir", "usbhs-d0", "usbhs-d1";
			num-bidir-endpoints = <10>;
			phys = <&usbhs_phy>;
			status = "disabled";
			udc {
				compatible = "renesas,ra-udc";
				status = "disabled";
			};
		};
	};

	usbhs_phy: usbhs-phy {
		compatible = "renesas,ra-usbphyc";
		#phy-cells = <0>;
	};
};

&ioport0 {
	port-irqs = <&port_irq6 &port_irq7 &port_irq8
	&port_irq9 &port_irq10 &port_irq11
	&port_irq12 &port_irq13 &port_irq14>;
	port-irq-names = "port-irq6",
			 "port-irq7",
			 "port-irq8",
			 "port-irq9",
			 "port-irq10",
			 "port-irq11",
			 "port-irq12",
			 "port-irq13",
			 "port-irq14";
	port-irq6-pins = <0>;
	port-irq7-pins = <1>;
	port-irq8-pins = <2>;
	port-irq9-pins = <4>;
	port-irq10-pins = <5>;
	port-irq11-pins = <6>;
	port-irq12-pins = <8>;
	port-irq13-pins = <9 15>;
	port-irq14-pins = <10>;
};

&ioport1 {
	port-irqs = <&port_irq0 &port_irq1 &port_irq2>;
	port-irq-names = "port-irq0",
			 "port-irq1",
			 "port-irq2";
	port-irq0-pins = <5>;
	port-irq1-pins = <1 4>;
	port-irq2-pins = <0>;
};

&ioport2 {
	port-irqs = <&port_irq0 &port_irq1 &port_irq2
	&port_irq3>;
	port-irq-names = "port-irq0",
			 "port-irq1",
			 "port-irq2",
			 "port-irq3";
	port-irq0-pins = <6>;
	port-irq1-pins = <5>;
	port-irq2-pins = <3 13>;
	port-irq3-pins = <2 8 12>;
};

&ioport3 {
	port-irqs = <&port_irq4 &port_irq5 &port_irq6
	&port_irq8 &port_irq9>;
	port-irq-names = "port-irq4",
			 "port-irq5",
			 "port-irq6",
			 "port-irq8",
			 "port-irq9";
	port-irq4-pins = <0>;
	port-irq5-pins = <2>;
	port-irq6-pins = <1>;
	port-irq8-pins = <5>;
	port-irq9-pins = <4>;
};

&ioport4 {
	port-irqs = <&port_irq0 &port_irq4 &port_irq5
	&port_irq6 &port_irq7 &port_irq8
	&port_irq9 &port_irq14 &port_irq15>;
	port-irq-names = "port-irq0",
			 "port-irq4",
			 "port-irq5",
			 "port-irq6",
			 "port-irq7",
			 "port-irq8",
			 "port-irq9",
			 "port-irq14",
			 "port-irq15";
	port-irq0-pins = <0>;
	port-irq4-pins = <2 11>;
	port-irq5-pins = <1 10>;
	port-irq6-pins = <9>;
	port-irq7-pins = <8>;
	port-irq8-pins = <15>;
	port-irq9-pins = <14>;
	port-irq14-pins = <3>;
	port-irq15-pins = <4>;
};

&ioport5 {
	port-irqs = <&port_irq1 &port_irq2 &port_irq3
	&port_irq14 &port_irq15>;
	port-irq-names = "port-irq1",
			 "port-irq2",
			 "port-irq3",
			 "port-irq14",
			 "port-irq15";
	port-irq1-pins = <8>;
	port-irq2-pins = <9>;
	port-irq3-pins = <10>;
	port-irq14-pins = <12>;
	port-irq15-pins = <11>;
};

&ioport6 {
	port-irqs = <&port_irq7>;
	port-irq-names = "port-irq7";
	port-irq7-pins = <15>;
};

&ioport7 {
	port-irqs = <&port_irq7 &port_irq8 &port_irq10
	&port_irq11>;
	port-irq-names = "port-irq7",
			 "port-irq8",
			 "port-irq10",
			 "port-irq11";
	port-irq7-pins = <6>;
	port-irq8-pins = <7>;
	port-irq10-pins = <9>;
	port-irq11-pins = <8>;
};

&ioport8 {
	port-irqs = <&port_irq0 &port_irq11 &port_irq12
	&port_irq14 &port_irq15>;
	port-irq-names = "port-irq0",
			 "port-irq11",
			 "port-irq12",
			 "port-irq14",
			 "port-irq15";
	port-irq0-pins = <6>;
	port-irq11-pins = <0>;
	port-irq12-pins = <1>;
	port-irq14-pins = <4>;
	port-irq15-pins = <8>;
};

&ioport9 {
	port-irqs = <&port_irq8 &port_irq9 &port_irq10
	&port_irq11>;
	port-irq-names = "port-irq8",
			 "port-irq9",
			 "port-irq10",
			 "port-irq11";
	port-irq8-pins = <5>;
	port-irq9-pins = <6>;
	port-irq10-pins = <7>;
	port-irq11-pins = <8>;
};

&ioporta {
	port-irqs = <&port_irq4 &port_irq5 &port_irq6>;
	port-irq-names = "port-irq4",
			 "port-irq5",
			 "port-irq6";
	port-irq4-pins = <10>;
	port-irq5-pins = <9>;
	port-irq6-pins = <8>;
};