Lines Matching +full:pll +full:- +full:clock +full:- +full:cells

2 # SPDX-License-Identifier: Apache-2.0
5   STM32F2 Main PLL node binding:
7   Takes one of clk_hse or clk_hsi as input clock.
9   Up to 2 output clocks could be supported and for each output clock, the
12     f(PLL_P) = f(VCO clock) / PLLP  --> PLLCLK (System Clock)
13     f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48CLK (Optional)
15       with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
17   The PLL output frequency must not exceed 168 MHz.
20 compatible: "st,stm32f2-pll-clock"
22 include: [clock-controller.yaml, base.yaml]
25   "#clock-cells":
31   div-m:
35         Division factor for the PLL input clock
36         Valid range: 2 - 63
38   mul-n:
42         PLL multiplication factor for VCO
43         Valid range: 192 - 432
45   div-p:
49         PLL division factor for PLLCLK
51       - 2
52       - 4
53       - 6
54       - 8
56   div-q:
59         PLL division factor for PLL48CK
60         Valid range: 2 - 15