1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8#include <zephyr/dt-bindings/clock/ra_clock.h>
9
10/delete-node/ &agt0;
11/delete-node/ &agt1;
12/delete-node/ &agt2;
13/delete-node/ &agt3;
14/delete-node/ &agt4;
15/delete-node/ &agt5;
16#include <zephyr/dt-bindings/pwm/ra_pwm.h>
17
18/delete-node/ &adc1;
19
20/ {
21	soc {
22		sram0: memory@20000000 {
23			compatible = "mmio-sram";
24			reg = <0x20000000 DT_SIZE_K(40)>;
25		};
26
27		ioport8: gpio@40080100 {
28			compatible = "renesas,ra-gpio-ioport";
29			reg = <0x40080100 0x20>;
30			port = <8>;
31			gpio-controller;
32			#gpio-cells = <2>;
33			ngpios = <16>;
34			status = "disabled";
35		};
36
37		adc@40170000 {
38			channel-count = <12>;
39			channel-available-mask = <0x139f7>;
40		};
41
42		id_code: id_code@100a120 {
43			compatible = "zephyr,memory-region";
44			reg = <0x0100a120 0x10>;
45			zephyr,memory-region = "ID_CODE";
46			status = "okay";
47		};
48
49		canfd_global: canfd_global@400b0000 {
50			compatible = "renesas,ra-canfd-global";
51			interrupts = <40 1>, <41 1>;
52			interrupt-names = "rxf", "glerr";
53			clocks = <&pclkb 0 0>, <&pclka 0 0>;
54			clock-names = "opclk", "ramclk";
55			reg = <0x400b0000 0x2000>;
56			status = "disabled";
57
58			canfd0: canfd0 {
59				compatible = "renesas,ra-canfd";
60				channel = <0>;
61				interrupts = <43 12>, <44 12>, <45 12>;
62				interrupt-names = "err", "tx", "rx";
63				clocks = <&canfdclk MSTPC 27>;
64				clock-names = "dllclk";
65				status = "disabled";
66			};
67		};
68
69		pwm0: pwm0@40169000 {
70			compatible = "renesas,ra-pwm";
71			divider = <RA_PWM_SOURCE_DIV_1>;
72			channel = <RA_PWM_CHANNEL_0>;
73			clocks = <&pclkd MSTPE 31>;
74			reg = <0x40169000 0x100>;
75			#pwm-cells = <3>;
76			status = "disabled";
77		};
78
79		pwm3: pwm3@40169300 {
80			compatible = "renesas,ra-pwm";
81			divider = <RA_PWM_SOURCE_DIV_1>;
82			channel = <RA_PWM_CHANNEL_3>;
83			clocks = <&pclkd MSTPE 28>;
84			reg = <0x40169300 0x100>;
85			#pwm-cells = <3>;
86			status = "disabled";
87		};
88
89		trng: trng {
90			compatible = "renesas,ra-trng";
91			status = "disabled";
92		};
93	};
94
95	clocks: clocks {
96		#address-cells = <1>;
97		#size-cells = <1>;
98
99		xtal: clock-main-osc {
100			compatible = "renesas,ra-cgc-external-clock";
101			clock-frequency = <DT_FREQ_M(20)>;
102			#clock-cells = <0>;
103			status = "disabled";
104		};
105
106		hoco: clock-hoco {
107			compatible = "fixed-clock";
108			clock-frequency = <DT_FREQ_M(20)>;
109			#clock-cells = <0>;
110		};
111
112		moco: clock-moco {
113			compatible = "fixed-clock";
114			clock-frequency = <DT_FREQ_M(8)>;
115			#clock-cells = <0>;
116		};
117
118		loco: clock-loco {
119			compatible = "fixed-clock";
120			clock-frequency = <32768>;
121			#clock-cells = <0>;
122		};
123
124		subclk: clock-subclk {
125			compatible = "renesas,ra-cgc-subclk";
126			clock-frequency = <32768>;
127			#clock-cells = <0>;
128			status = "disabled";
129		};
130
131		pll: pll {
132			compatible = "renesas,ra-cgc-pll";
133			#clock-cells = <0>;
134
135			/* PLL */
136			clocks = <&xtal>;
137			div = <1>;
138			mul = <10 0>;
139			status = "disabled";
140		};
141
142		pclkblock: pclkblock@40084000 {
143			compatible = "renesas,ra-cgc-pclk-block";
144			reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
145			      <0x4008400c 4>, <0x40084010 4>;
146			reg-names = "MSTPA", "MSTPB","MSTPC",
147				    "MSTPD", "MSTPE";
148			#clock-cells = <0>;
149			clocks = <&pll>;
150			status = "okay";
151
152			iclk: iclk {
153				compatible = "renesas,ra-cgc-pclk";
154				div = <1>;
155				#clock-cells = <2>;
156				status = "okay";
157			};
158
159			pclka: pclka {
160				compatible = "renesas,ra-cgc-pclk";
161				div = <2>;
162				#clock-cells = <2>;
163				status = "okay";
164			};
165
166			pclkb: pclkb {
167				compatible = "renesas,ra-cgc-pclk";
168				div = <4>;
169				#clock-cells = <2>;
170				status = "okay";
171			};
172
173			pclkc: pclkc {
174				compatible = "renesas,ra-cgc-pclk";
175				div = <4>;
176				#clock-cells = <2>;
177				status = "okay";
178			};
179
180			pclkd: pclkd {
181				compatible = "renesas,ra-cgc-pclk";
182				div = <2>;
183				#clock-cells = <2>;
184				status = "okay";
185			};
186
187			fclk: fclk {
188				compatible = "renesas,ra-cgc-pclk";
189				div = <4>;
190				#clock-cells = <2>;
191				status = "okay";
192			};
193
194			clkout: clkout {
195				compatible = "renesas,ra-cgc-pclk";
196				#clock-cells = <2>;
197				status = "disabled";
198			};
199
200			uclk: uclk {
201				compatible = "renesas,ra-cgc-pclk";
202				#clock-cells = <2>;
203				status = "disabled";
204			};
205
206			canfdclk: canfdclk {
207				compatible = "renesas,ra-cgc-pclk";
208				#clock-cells = <2>;
209				status = "disabled";
210			};
211
212			cecclk: cecclk {
213				compatible = "renesas,ra-cgc-pclk";
214				#clock-cells = <2>;
215				status = "disabled";
216			};
217
218			i3cclk: i3cclk {
219				compatible = "renesas,ra-cgc-pclk";
220				#clock-cells = <2>;
221				status = "disabled";
222			};
223		};
224	};
225};
226
227&ioport0 {
228	port-irqs = <&port_irq6 &port_irq7 &port_irq8
229	&port_irq9 &port_irq10 &port_irq11
230	&port_irq12 &port_irq13>;
231	port-irq-names = "port-irq6",
232			 "port-irq7",
233			 "port-irq8",
234			 "port-irq9",
235			 "port-irq10",
236			 "port-irq11",
237			 "port-irq12",
238			 "port-irq13";
239	port-irq6-pins = <0>;
240	port-irq7-pins = <1>;
241	port-irq8-pins = <2>;
242	port-irq9-pins = <4>;
243	port-irq10-pins = <5>;
244	port-irq11-pins = <6>;
245	port-irq12-pins = <8>;
246	port-irq13-pins = <15>;
247};
248
249&ioport1 {
250	port-irqs = <&port_irq0 &port_irq1 &port_irq2
251	&port_irq3 &port_irq4>;
252	port-irq-names = "port-irq0",
253			 "port-irq1",
254			 "port-irq2",
255			 "port-irq3",
256			 "port-irq4";
257	port-irq0-pins = <5>;
258	port-irq1-pins = <1 4>;
259	port-irq2-pins = <0>;
260	port-irq3-pins = <10>;
261	port-irq4-pins = <11>;
262};
263
264&ioport2 {
265	port-irqs = <&port_irq0 &port_irq1 &port_irq2
266	&port_irq3>;
267	port-irq-names = "port-irq0",
268			 "port-irq1",
269			 "port-irq2",
270			 "port-irq3";
271	port-irq0-pins = <6>;
272	port-irq1-pins = <5>;
273	port-irq2-pins = <13>;
274	port-irq3-pins = <12>;
275};
276
277&ioport3 {
278	port-irqs = <&port_irq5 &port_irq6 &port_irq9>;
279	port-irq-names = "port-irq5",
280			 "port-irq6",
281			 "port-irq9";
282	port-irq5-pins = <2>;
283	port-irq6-pins = <1>;
284	port-irq9-pins = <4>;
285};
286
287&ioport4 {
288	port-irqs = <&port_irq0 &port_irq4 &port_irq5
289	&port_irq6 &port_irq7 &port_irq14>;
290	port-irq-names = "port-irq0",
291			 "port-irq4",
292			 "port-irq5",
293			 "port-irq6",
294			 "port-irq7",
295			 "port-irq14";
296	port-irq0-pins = <0>;
297	port-irq4-pins = <2 11>;
298	port-irq5-pins = <1 10>;
299	port-irq6-pins = <9>;
300	port-irq7-pins = <8>;
301	port-irq14-pins = <3>;
302};
303
304&ioport8 {
305	port-irqs = <&port_irq11>;
306	port-irq-names = "port-irq11";
307	port-irq11-pins = <14>;
308};
309