Searched +full:stm32 +full:- +full:dma +full:- +full:v2 (Results 1 – 25 of 94) sorted by relevance
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| /Zephyr-latest/drivers/dma/ |
| D | Kconfig.stm32 | 1 # DMA configuration options
6 # SPDX-License-Identifier: Apache-2.0
9 bool "STM32 DMA driver"
17 Driver for STM32 DMA V1, V2, V2bis and BDMA types.
20 bool "STM32U5 serie DMA driver"
25 Enable DMA support mainly for stm32U5 family.
26 It differs from the DMA driver due to the GPDMA peripheral.
35 Enable DMA V1 support.
42 Enable DMA V2 or DMA V2bis support. With the versions V2 of DMA, the
43 peripheral request must be specified in the dma slot of the dma cell
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| /Zephyr-latest/dts/bindings/dma/ |
| D | st,stm32-dma-v2.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller (V2)
7 It is present on stm32 devices like stm32L4 or stm32WB.
8 This DMA controller includes several channels with different requests.
9 DMA clients connected to the STM32 DMA controller must use the format
10 described in the dma.txt file, using a four-cell specifier for each
11 capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a 3-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
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| D | st,stm32-dma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller
7 The STM32 DMA is a general-purpose direct memory access controller
8 capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
9 Each stm32 soc with a DMA is of a special version type, which could be
11 or V2 like stm32L4 soc or stm322WB, some also have DMAMUX controller
14 compatible: "st,stm32-dma"
16 include: dma-controller.yaml
27 description: If the DMA controller V1 supports memory to memory transfer
29 dma-offset:
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| D | st,stm32-dmamux.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMAMUX controller
7 The STM32 DMAMUX is a direct memory access multiplexer
8 capable of supporting independent DMA channels.
9 DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
10 for each dmamux channel: a phandle to the DMA multiplexer plus the following 2 integer cells:
11 1. channel: the mux channel from 0 to <dma-channels> - 1
13 3. channel-config: A 32bit mask specifying the DMA channel configuration
15 -bit 6-7 : Direction (see dma.h)
20 -bit 9 : Peripheral Increment Address
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| /Zephyr-latest/dts/arm/st/u0/ |
| D | stm32u073.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32u073", "st,stm32u0", "simple-bus";
14 compatible = "st,stm32-i2c-v2";
15 clock-frequency = <I2C_BITRATE_STANDARD>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 interrupt-names = "combined";
26 compatible = "st,stm32-lptim";
28 #address-cells = <1>;
29 #size-cells = <0>;
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| D | stm32u0.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/clock/stm32u0_clock.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/adc/adc.h>
12 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/i2c/i2c.h>
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| /Zephyr-latest/dts/arm/st/g0/ |
| D | stm32g0b0.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g0b0", "st,stm32g0", "simple-bus";
13 pinctrl: pin-controller@50000000 {
15 compatible = "st,stm32-gpio";
16 gpio-controller;
17 #gpio-cells = <2>;
24 compatible = "st,stm32-usart", "st,stm32-uart";
33 compatible = "st,stm32-usart", "st,stm32-uart";
42 compatible = "st,stm32-timers";
47 interrupt-names = "global";
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| D | stm32g0b1.dtsi | 3 * Copyright (c) 2021 G-Technologies Sdn. Bhd.
5 * SPDX-License-Identifier: Apache-2.0
13 clk_hsi48: clk-hsi48 {
14 #clock-cells = <0>;
15 compatible = "st,stm32-hsi48-clock";
16 clock-frequency = <DT_FREQ_M(48)>;
22 compatible = "st,stm32g0b1", "st,stm32g0", "simple-bus";
25 pinctrl: pin-controller@50000000 {
27 compatible = "st,stm32-gpio";
28 gpio-controller;
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| D | stm32g0.dtsi | 3 * Copyright (c) 2019-2024 STMicroelectronics
6 * Copyright (c) 2021 G-Technologies Sdn. Bhd.
8 * SPDX-License-Identifier: Apache-2.0
11 #include <arm/armv6-m.dtsi>
12 #include <zephyr/dt-bindings/clock/stm32g0_clock.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/adc.h>
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| /Zephyr-latest/dts/arm/st/c0/ |
| D | stm32c071.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32c071", "st,stm32c0", "simple-bus";
14 compatible = "st,stm32-timers";
19 interrupt-names = "global";
24 compatible = "st,stm32-pwm";
26 #pwm-cells = <3>;
30 compatible = "st,stm32-counter";
36 compatible = "st,stm32-i2c-v2";
37 clock-frequency = <I2C_BITRATE_STANDARD>;
38 #address-cells = <1>;
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| D | stm32c0.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/stm32c0_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/dma/stm32_dma.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
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| /Zephyr-latest/dts/arm/st/wl/ |
| D | stm32wl.dtsi | 2 * Copyright (c) 2020-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/clock/stm32wl_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/lora/sx126x.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/adc/adc.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
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| /Zephyr-latest/dts/arm/st/wb/ |
| D | stm32wb.dtsi | 6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32wb_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/adc/adc.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
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| /Zephyr-latest/dts/arm/st/l4/ |
| D | stm32l4.dtsi | 6 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/clock/stm32l4_clock.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/adc/adc.h>
16 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
17 #include <zephyr/dt-bindings/dma/stm32_dma.h>
18 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
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| D | stm32l4p5.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/flash_controller/ospi.h>
11 /delete-node/ &quadspi;
26 clk_hsi48: clk-hsi48 {
27 #clock-cells = <0>;
28 compatible = "fixed-clock";
29 clock-frequency = <DT_FREQ_M(48)>;
35 compatible = "st,stm32l4p5", "st,stm32l4", "simple-bus";
38 flash-controller@40022000 {
40 erase-block-size = <4096>;
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| /Zephyr-latest/dts/arm/st/g4/ |
| D | stm32g4.dtsi | 6 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/clock/stm32g4_clock.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/adc/adc.h>
16 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
17 #include <zephyr/dt-bindings/dma/stm32_dma.h>
18 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
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| /Zephyr-latest/dts/arm/st/l5/ |
| D | stm32l5.dtsi | 6 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv8-m.dtsi>
11 #include <zephyr/dt-bindings/clock/stm32l4_clock.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
18 #include <zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h>
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| /Zephyr-latest/dts/arm/st/wb0/ |
| D | stm32wb0.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/clock/stm32wb0_clock.h>
13 #include <zephyr/dt-bindings/reset/stm32wb0_reset.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
25 zephyr,flash-controller = &flash;
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| /Zephyr-latest/dts/arm/st/h7/ |
| D | stm32h7.dtsi | 7 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/clock/stm32h7_clock.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/stm32h7_adc.h>
18 #include <zephyr/dt-bindings/reset/stm32h7_reset.h>
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| /Zephyr-latest/dts/arm/st/mp1/ |
| D | stm32mp157.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/clock/stm32_common_clocks.h>
13 #include <zephyr/dt-bindings/clock/stm32_clock.h>
14 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
17 #include <zephyr/dt-bindings/dma/stm32_dma.h>
18 #include <zephyr/dt-bindings/reset/stm32mp1_reset.h>
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| /Zephyr-latest/dts/arm/st/l0/ |
| D | stm32l0.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/clock/stm32l0_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/adc/adc.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
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| /Zephyr-latest/dts/arm/st/h5/ |
| D | stm32h5.dtsi | 2 * Copyright (c) 2023-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/stm32h5_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/reset/stm32h5_reset.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
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| /Zephyr-latest/dts/arm/st/wba/ |
| D | stm32wba.dtsi | 2 * Copyright (c) 2023-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
10 #include <zephyr/dt-bindings/clock/stm32wba_clock.h>
11 #include <zephyr/dt-bindings/reset/stm32wba_reset.h>
12 #include <zephyr/dt-bindings/adc/stm32u5_adc.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
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| /Zephyr-latest/dts/arm/st/f7/ |
| D | stm32f7.dtsi | 6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32f7_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32f4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h>
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| /Zephyr-latest/dts/arm/st/f0/ |
| D | stm32f0.dtsi | 6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv6-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32f0_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32f0_1_3_reset.h>
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