Lines Matching +full:stm32 +full:- +full:dma +full:- +full:v2
6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv6-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32f0_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32f0_1_3_reset.h>
18 #include <zephyr/dt-bindings/adc/adc.h>
23 zephyr,flash-controller = &flash;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 compatible = "arm,cortex-m0";
38 compatible = "mmio-sram";
42 clk_hse: clk-hse {
43 #clock-cells = <0>;
44 compatible = "st,stm32-hse-clock";
48 clk_hsi: clk-hsi {
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <DT_FREQ_M(8)>;
55 clk_hsi14: clk-hsi14 {
56 #clock-cells = <0>;
57 compatible = "fixed-clock";
58 clock-frequency = <DT_FREQ_M(14)>;
62 clk_lse: clk-lse {
63 #clock-cells = <0>;
64 compatible = "st,stm32-lse-clock";
65 clock-frequency = <32768>;
66 driving-capability = <0>;
70 clk_lsi: clk-lsi {
71 #clock-cells = <0>;
72 compatible = "fixed-clock";
73 clock-frequency = <DT_FREQ_K(40)>;
78 #clock-cells = <0>;
79 compatible = "st,stm32f0-pll-clock";
85 flash: flash-controller@40022000 {
86 compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
91 #address-cells = <1>;
92 #size-cells = <1>;
95 compatible = "st,stm32-nv-flash", "soc-nv-flash";
96 erase-block-size = <1024>;
97 write-block-size = <2>;
99 max-erase-time = <40>;
104 compatible = "st,stm32f0-rcc";
105 #clock-cells = <2>;
108 rctl: reset-controller {
109 compatible = "st,stm32-rcc-rctl";
110 #reset-cells = <1>;
114 exti: interrupt-controller@40010400 {
115 compatible = "st,stm32-exti";
116 interrupt-controller;
117 #interrupt-cells = <1>;
118 #address-cells = <1>;
120 num-lines = <16>;
122 interrupt-names = "line0-1", "line2-3", "line4-15";
123 line-ranges = <0 2>, <2 2>, <4 12>;
126 pinctrl: pin-controller@48000000 {
127 compatible = "st,stm32-pinctrl";
128 #address-cells = <1>;
129 #size-cells = <1>;
133 compatible = "st,stm32-gpio";
134 gpio-controller;
135 #gpio-cells = <2>;
141 compatible = "st,stm32-gpio";
142 gpio-controller;
143 #gpio-cells = <2>;
149 compatible = "st,stm32-gpio";
150 gpio-controller;
151 #gpio-cells = <2>;
157 compatible = "st,stm32-gpio";
158 gpio-controller;
159 #gpio-cells = <2>;
165 compatible = "st,stm32-gpio";
166 gpio-controller;
167 #gpio-cells = <2>;
174 compatible = "st,stm32-usart", "st,stm32-uart";
183 compatible = "st,stm32-i2c-v2";
184 clock-frequency = <I2C_BITRATE_STANDARD>;
185 #address-cells = <1>;
186 #size-cells = <0>;
194 interrupt-names = "combined";
199 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
200 #address-cells = <1>;
201 #size-cells = <0>;
209 compatible = "st,stm32-rtc";
214 alarms-count = <1>;
215 alrm-exti-line = <17>;
220 compatible = "st,stm32-watchdog";
226 compatible = "st,stm32-window-watchdog";
234 compatible = "st,stm32-timers";
239 interrupt-names = "brk_up_trg_com", "cc";
244 compatible = "st,stm32-pwm";
246 #pwm-cells = <3>;
251 compatible = "st,stm32-timers";
256 interrupt-names = "global";
261 compatible = "st,stm32-pwm";
263 #pwm-cells = <3>;
267 compatible = "st,stm32-counter";
273 compatible = "st,stm32-timers";
278 interrupt-names = "global";
283 compatible = "st,stm32-pwm";
285 #pwm-cells = <3>;
289 compatible = "st,stm32-counter";
295 compatible = "st,stm32-timers";
300 interrupt-names = "global";
305 compatible = "st,stm32-pwm";
307 #pwm-cells = <3>;
311 compatible = "st,stm32-counter";
317 compatible = "st,stm32-timers";
322 interrupt-names = "global";
327 compatible = "st,stm32-pwm";
329 #pwm-cells = <3>;
333 compatible = "st,stm32-counter";
339 compatible = "st,stm32-adc";
344 #io-channel-cells = <1>;
349 sampling-times = <2 8 14 29 42 56 72 240>;
350 num-sampling-time-common-channels = <1>;
351 st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
352 st,adc-oversampler = "OVERSAMPLER_NONE";
355 dma1: dma@40020000 {
356 compatible = "st,stm32-dma-v2bis";
357 #dma-cells = <2>;
366 compatible = "st,stm32-vref";
367 vrefint-cal-addr = <0x1FFFF7BA>;
368 vrefint-cal-mv = <3300>;
369 io-channels = <&adc1 17>;
374 compatible = "st,stm32-smbus";
375 #address-cells = <1>;
376 #size-cells = <0>;
383 arm,num-irq-priority-bits = <2>;