1/* 2 * Copyright (c) 2023-2024 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 8#include <arm/armv8-m.dtsi> 9#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> 10#include <zephyr/dt-bindings/clock/stm32wba_clock.h> 11#include <zephyr/dt-bindings/reset/stm32wba_reset.h> 12#include <zephyr/dt-bindings/adc/stm32u5_adc.h> 13#include <zephyr/dt-bindings/gpio/gpio.h> 14#include <zephyr/dt-bindings/i2c/i2c.h> 15#include <zephyr/dt-bindings/pwm/pwm.h> 16#include <zephyr/dt-bindings/adc/adc.h> 17#include <zephyr/dt-bindings/dma/stm32_dma.h> 18 19#include <freq.h> 20 21/ { 22 chosen { 23 zephyr,entropy = &rng; 24 zephyr,flash-controller = &flash; 25 st,lptim-stdby-timer = &rtc; 26 zephyr,bt-hci = &bt_hci_wba; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-m33"; 36 reg = <0>; 37 /* Do not add &standby here since CONFIG_PM_S2RAM is disabled by default */ 38 cpu-power-states = <&stop0 &stop1>; 39 #address-cells = <1>; 40 #size-cells = <1>; 41 42 mpu: mpu@e000ed90 { 43 compatible = "arm,armv8m-mpu"; 44 reg = <0xe000ed90 0x40>; 45 }; 46 }; 47 48 power-states { 49 stop0: state0 { 50 compatible = "zephyr,power-state"; 51 power-state-name = "suspend-to-idle"; 52 substate-id = <1>; 53 min-residency-us = <100>; 54 }; 55 stop1: state1 { 56 compatible = "zephyr,power-state"; 57 power-state-name = "suspend-to-idle"; 58 substate-id = <2>; 59 min-residency-us = <500>; 60 }; 61 standby: state2 { 62 compatible = "zephyr,power-state"; 63 power-state-name = "suspend-to-ram"; 64 substate-id = <1>; 65 min-residency-us = <1000>; 66 exit-latency-us = <50>; 67 }; 68 }; 69 }; 70 71 sram0: memory@20000000 { 72 compatible = "mmio-sram"; 73 }; 74 75 /* Defining this memory solves unaligned memory access issue */ 76 sram6: memory@48028000 { 77 compatible = "zephyr,memory-region", "mmio-sram"; 78 reg = <0x48028000 DT_SIZE_K(16)>; 79 device_type = "memory"; 80 zephyr,memory-region = "SRAM6"; 81 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; 82 }; 83 84 clocks { 85 clk_hse: clk-hse { 86 #clock-cells = <0>; 87 compatible = "st,stm32wba-hse-clock"; 88 clock-frequency = <DT_FREQ_M(32)>; 89 status = "disabled"; 90 }; 91 92 clk_hsi: clk-hsi { 93 #clock-cells = <0>; 94 compatible = "fixed-clock"; 95 clock-frequency = <DT_FREQ_M(16)>; 96 status = "disabled"; 97 }; 98 99 clk_lse: clk-lse { 100 #clock-cells = <0>; 101 compatible = "st,stm32-lse-clock"; 102 clock-frequency = <32768>; 103 driving-capability = <1>; 104 status = "disabled"; 105 }; 106 107 clk_lsi: clk-lsi { 108 #clock-cells = <0>; 109 compatible = "fixed-clock"; 110 clock-frequency = <DT_FREQ_K(32)>; 111 status = "disabled"; 112 }; 113 114 pll1: pll: pll { 115 #clock-cells = <0>; 116 compatible = "st,stm32wba-pll-clock"; 117 status = "disabled"; 118 }; 119 }; 120 121 soc { 122 flash: flash-controller@40022000 { 123 compatible = "st,stm32-flash-controller", "st,stm32wba-flash-controller"; 124 reg = <0x40022000 0x400>; 125 interrupts = <6 0>; 126 127 #address-cells = <1>; 128 #size-cells = <1>; 129 130 flash0: flash@8000000 { 131 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 132 133 write-block-size = <16>; 134 erase-block-size = <8192>; 135 /* maximum erase time(ms) for a 8K sector */ 136 max-erase-time = <5>; 137 }; 138 }; 139 140 rcc: rcc@46020c00 { 141 compatible = "st,stm32wba-rcc"; 142 clocks-controller; 143 #clock-cells = <2>; 144 reg = <0x46020c00 0x400>; 145 146 rctl: reset-controller { 147 compatible = "st,stm32-rcc-rctl"; 148 #reset-cells = <1>; 149 }; 150 }; 151 152 exti: interrupt-controller@46022000 { 153 compatible = "st,stm32g0-exti", "st,stm32-exti"; 154 interrupt-controller; 155 #interrupt-cells = <1>; 156 reg = <0x46022000 0x400>; 157 num-lines = <16>; 158 interrupts = <11 0>, <12 0>, <13 0>, <14 0>, 159 <15 0>, <16 0>, <17 0>, <18 0>, 160 <19 0>, <20 0>, <21 0>, <22 0>, 161 <23 0>, <24 0>, <25 0>, <26 0>; 162 interrupt-names = "line0", "line1", "line2", "line3", 163 "line4", "line5", "line6", "line7", 164 "line8", "line9", "line10", "line11", 165 "line12", "line13", "line14", "line15"; 166 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 167 <4 1>, <5 1>, <6 1>, <7 1>, 168 <8 1>, <9 1>, <10 1>, <11 1>, 169 <12 1>, <13 1>, <14 1>, <15 1>; 170 }; 171 172 pinctrl: pin-controller@42020000 { 173 compatible = "st,stm32-pinctrl"; 174 #address-cells = <1>; 175 #size-cells = <1>; 176 reg = <0x42020000 0x2000>; 177 178 gpioa: gpio@42020000 { 179 compatible = "st,stm32-gpio"; 180 gpio-controller; 181 #gpio-cells = <2>; 182 reg = <0x42020000 0x400>; 183 clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; 184 }; 185 186 gpiob: gpio@42020400 { 187 compatible = "st,stm32-gpio"; 188 gpio-controller; 189 #gpio-cells = <2>; 190 reg = <0x42020400 0x400>; 191 clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; 192 }; 193 194 gpioc: gpio@42020800 { 195 compatible = "st,stm32-gpio"; 196 gpio-controller; 197 #gpio-cells = <2>; 198 reg = <0x42020800 0x400>; 199 clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; 200 }; 201 202 gpioh: gpio@42021c00 { 203 compatible = "st,stm32-gpio"; 204 gpio-controller; 205 #gpio-cells = <2>; 206 reg = <0x42021c00 0x400>; 207 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; 208 }; 209 }; 210 211 rtc: rtc@46007800 { 212 compatible = "st,stm32-rtc"; 213 reg = <0x46007800 0x400>; 214 interrupts = <2 0>; 215 clocks = <&rcc STM32_CLOCK(APB7, 21U)>; 216 alarms-count = <2>; 217 status = "disabled"; 218 }; 219 220 iwdg: watchdog@40003000 { 221 compatible = "st,stm32-watchdog"; 222 reg = <0x40003000 0x400>; 223 status = "disabled"; 224 }; 225 226 wwdg: watchdog@40002c00 { 227 compatible = "st,stm32-window-watchdog"; 228 reg = <0x40002C00 0x400>; 229 clocks = <&rcc STM32_CLOCK(APB1, 11U)>; 230 interrupts = <0 7>; 231 status = "disabled"; 232 }; 233 234 usart1: serial@40013800 { 235 compatible = "st,stm32-usart", "st,stm32-uart"; 236 reg = <0x40013800 0x400>; 237 clocks = <&rcc STM32_CLOCK(APB2, 14U)>; 238 resets = <&rctl STM32_RESET(APB2, 14U)>; 239 interrupts = <46 0>; 240 status = "disabled"; 241 }; 242 243 usart2: serial@40004400 { 244 compatible = "st,stm32-usart", "st,stm32-uart"; 245 reg = <0x40004400 0x400>; 246 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 247 resets = <&rctl STM32_RESET(APB1L, 17U)>; 248 interrupts = <47 0>; 249 status = "disabled"; 250 }; 251 252 lpuart1: serial@46002400 { 253 compatible = "st,stm32-lpuart", "st,stm32-uart"; 254 reg = <0x46002400 0x400>; 255 clocks = <&rcc STM32_CLOCK(APB7, 6U)>; 256 resets = <&rctl STM32_RESET(APB7, 6U)>; 257 interrupts = <48 0>; 258 status = "disabled"; 259 }; 260 261 spi1: spi@40013000 { 262 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 reg = <0x40013000 0x400>; 266 interrupts = <45 5>; 267 clocks = <&rcc STM32_CLOCK(APB2, 12U)>; 268 status = "disabled"; 269 }; 270 271 spi3: spi@46002000 { 272 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 reg = <0x46002000 0x400>; 276 interrupts = <63 5>; 277 clocks = <&rcc STM32_CLOCK(APB7, 5U)>; 278 status = "disabled"; 279 }; 280 281 i2c1: i2c@40005400 { 282 compatible = "st,stm32-i2c-v2"; 283 clock-frequency = <I2C_BITRATE_STANDARD>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 reg = <0x40005400 0x400>; 287 clocks = <&rcc STM32_CLOCK(APB1, 21U)>; 288 interrupts = <43 0>, <44 0>; 289 interrupt-names = "event", "error"; 290 status = "disabled"; 291 }; 292 293 i2c3: i2c@46002800 { 294 compatible = "st,stm32-i2c-v2"; 295 clock-frequency = <I2C_BITRATE_STANDARD>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 reg = <0x46002800 0x400>; 299 clocks = <&rcc STM32_CLOCK(APB7, 7U)>; 300 interrupts = <54 0>, <55 0>; 301 interrupt-names = "event", "error"; 302 status = "disabled"; 303 }; 304 305 timers1: timers@40012c00 { 306 compatible = "st,stm32-timers"; 307 reg = <0x40012c00 0x400>; 308 clocks = <&rcc STM32_CLOCK(APB2, 11U)>; 309 resets = <&rctl STM32_RESET(APB2, 11U)>; 310 interrupts = <37 0>, <38 0>, <39 0>, <40 0>; 311 interrupt-names = "brk", "up", "trgcom", "cc"; 312 st,prescaler = <0>; 313 status = "disabled"; 314 315 counter { 316 compatible = "st,stm32-counter"; 317 status = "disabled"; 318 }; 319 320 pwm { 321 compatible = "st,stm32-pwm"; 322 status = "disabled"; 323 #pwm-cells = <3>; 324 }; 325 }; 326 327 timers2: timers@40000000 { 328 compatible = "st,stm32-timers"; 329 reg = <0x40000000 0x400>; 330 clocks = <&rcc STM32_CLOCK(APB1, 0U)>; 331 resets = <&rctl STM32_RESET(APB1L, 0U)>; 332 interrupts = <41 0>; 333 interrupt-names = "global"; 334 st,prescaler = <0>; 335 status = "disabled"; 336 337 counter { 338 compatible = "st,stm32-counter"; 339 status = "disabled"; 340 }; 341 342 pwm { 343 compatible = "st,stm32-pwm"; 344 status = "disabled"; 345 #pwm-cells = <3>; 346 }; 347 }; 348 349 timers3: timers@40000400 { 350 compatible = "st,stm32-timers"; 351 reg = <0x40000400 0x400>; 352 clocks = <&rcc STM32_CLOCK(APB1, 1U)>; 353 resets = <&rctl STM32_RESET(APB1L, 1U)>; 354 interrupts = <42 0>; 355 interrupt-names = "global"; 356 st,prescaler = <0>; 357 status = "disabled"; 358 359 counter { 360 compatible = "st,stm32-counter"; 361 status = "disabled"; 362 }; 363 364 pwm { 365 compatible = "st,stm32-pwm"; 366 status = "disabled"; 367 #pwm-cells = <3>; 368 }; 369 }; 370 371 timers16: timers@40014400 { 372 compatible = "st,stm32-timers"; 373 reg = <0x40014400 0x400>; 374 clocks = <&rcc STM32_CLOCK(APB2, 17U)>; 375 resets = <&rctl STM32_RESET(APB2, 17U)>; 376 interrupts = <51 0>; 377 interrupt-names = "global"; 378 status = "disabled"; 379 380 counter { 381 compatible = "st,stm32-counter"; 382 status = "disabled"; 383 }; 384 385 pwm { 386 compatible = "st,stm32-pwm"; 387 status = "disabled"; 388 #pwm-cells = <3>; 389 }; 390 }; 391 392 timers17: timers@40014800 { 393 compatible = "st,stm32-timers"; 394 reg = <0x40014800 0x400>; 395 clocks = <&rcc STM32_CLOCK(APB2, 18U)>; 396 resets = <&rctl STM32_RESET(APB2, 18U)>; 397 interrupts = <52 0>; 398 interrupt-names = "global"; 399 status = "disabled"; 400 401 counter { 402 compatible = "st,stm32-counter"; 403 status = "disabled"; 404 }; 405 406 pwm { 407 compatible = "st,stm32-pwm"; 408 status = "disabled"; 409 #pwm-cells = <3>; 410 }; 411 }; 412 413 adc4: adc@46021000 { 414 compatible = "st,stm32-adc"; 415 reg = <0x46021000 0x400>; 416 clocks = <&rcc STM32_CLOCK(AHB4, 5U)>, 417 <&rcc STM32_SRC_HCLK1 ADC_SEL(0)>; 418 interrupts = <65 0>; 419 status = "disabled"; 420 #io-channel-cells = <1>; 421 resolutions = <STM32_ADC_RES(12, 0x00) 422 STM32_ADC_RES(10, 0x01) 423 STM32_ADC_RES(8, 0x02) 424 STM32_ADC_RES(6, 0x03)>; 425 sampling-times = <2 4 8 13 20 40 80 815>; 426 num-sampling-time-common-channels = <2>; 427 st,adc-clock-source = "ASYNC"; 428 st,adc-sequencer = "NOT_FULLY_CONFIGURABLE"; 429 st,adc-oversampler = "OVERSAMPLER_MINIMAL"; 430 }; 431 432 lptim1: timers@46004400 { 433 compatible = "st,stm32-lptim"; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 reg = <0x46004400 0x400>; 437 clocks = <&rcc STM32_CLOCK(APB7, 11U)>; 438 interrupts = <49 1>; 439 interrupt-names = "wakeup"; 440 status = "disabled"; 441 }; 442 443 lptim2: timers@40009400 { 444 compatible = "st,stm32-lptim"; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 reg = <0x40009400 0x400>; 448 clocks = <&rcc STM32_CLOCK(APB1_2, 5U)>; 449 interrupts = <50 1>; 450 interrupt-names = "wakeup"; 451 status = "disabled"; 452 }; 453 454 rng: rng@420c0800 { 455 compatible = "st,stm32-rng"; 456 reg = <0x420c0800 0x400>; 457 interrupts = <59 0>; 458 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>, 459 <&rcc STM32_SRC_HSI16 RNG_SEL(2)>; 460 nist-config = <0xf00d>; 461 health-test-config = <0xaac7>; 462 status = "disabled"; 463 }; 464 465 gpdma1: dma@40020000 { 466 compatible = "st,stm32u5-dma"; 467 #dma-cells = <3>; 468 reg = <0x40020000 0x1000>; 469 interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0>; 470 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; 471 dma-channels = <8>; 472 dma-requests = <52>; 473 dma-offset = <0>; 474 status = "disabled"; 475 }; 476 }; 477 478 die_temp: dietemp { 479 compatible = "st,stm32-temp-cal"; 480 ts-cal1-addr = <0x0BF90710>; 481 ts-cal2-addr = <0x0BF90742>; 482 ts-cal1-temp = <30>; 483 ts-cal2-temp = <130>; 484 ts-cal-vrefanalog = <3000>; 485 io-channels = <&adc4 13>; 486 status = "disabled"; 487 }; 488 489 bt_hci_wba: bt_hci_wba { 490 compatible = "st,hci-stm32wba"; 491 status = "okay"; 492 }; 493 494 swj_port: swj_port { 495 compatible = "swj-connector"; 496 pinctrl-0 = <&debug_jtms_swdio_pa13 &debug_jtck_swclk_pa14 497 &debug_jtdi_pa15 &debug_jtdo_swo_pb3 498 &debug_jtrst_pb4>; 499 pinctrl-1 = <&analog_pa13 &analog_pa14 &analog_pa15 500 &analog_pb3 &analog_pb4>; 501 pinctrl-names = "default", "sleep"; 502 }; 503 504 smbus1: smbus1 { 505 compatible = "st,stm32-smbus"; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 i2c = <&i2c1>; 509 status = "disabled"; 510 }; 511 512 smbus3: smbus3 { 513 compatible = "st,stm32-smbus"; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 i2c = <&i2c3>; 517 status = "disabled"; 518 }; 519}; 520 521&nvic { 522 arm,num-irq-priority-bits = <4>; 523}; 524
