1/*
2 * Copyright (c) 2018 Pushpal Sidhu
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <st/l4/stm32l4.dtsi>
9#include <zephyr/dt-bindings/flash_controller/ospi.h>
10
11/delete-node/ &quadspi;
12
13/ {
14	/* total SRAM 320KB for the stm32L4P5x and stm32L4Q5x */
15	sram0: memory@20000000 {
16		reg = <0x20000000 DT_SIZE_K(128)>;
17	};
18	sram1: memory@10000000 {
19		reg = <0x10000000 DT_SIZE_K(64)>;
20	};
21	sram2: memory@20030000 {
22		reg = <0x20030000 DT_SIZE_K(128)>;
23	};
24
25	clocks {
26		clk_hsi48: clk-hsi48 {
27			#clock-cells = <0>;
28			compatible = "fixed-clock";
29			clock-frequency = <DT_FREQ_M(48)>;
30			status = "disabled";
31		};
32	};
33
34	soc {
35		compatible = "st,stm32l4p5", "st,stm32l4", "simple-bus";
36
37
38		flash-controller@40022000 {
39			flash0: flash@8000000 {
40				erase-block-size = <4096>;
41			};
42		};
43
44		rcc: rcc@40021000 {
45			undershoot-prevention;
46		};
47
48		rng: rng@50060800 {
49			clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
50				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
51		};
52
53		pinctrl: pin-controller@48000000 {
54			reg = <0x48000000 0x2400>;
55
56			gpiod: gpio@48000c00 {
57				compatible = "st,stm32-gpio";
58				gpio-controller;
59				#gpio-cells = <2>;
60				reg = <0x48000c00 0x400>;
61				clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
62			};
63
64			gpioe: gpio@48001000 {
65				compatible = "st,stm32-gpio";
66				gpio-controller;
67				#gpio-cells = <2>;
68				reg = <0x48001000 0x400>;
69				clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
70			};
71
72			gpiof: gpio@48001400 {
73				compatible = "st,stm32-gpio";
74				gpio-controller;
75				#gpio-cells = <2>;
76				reg = <0x48001400 0x400>;
77				clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
78			};
79
80			gpiog: gpio@48001800 {
81				compatible = "st,stm32-gpio";
82				gpio-controller;
83				#gpio-cells = <2>;
84				reg = <0x48001800 0x400>;
85				clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
86			};
87
88			gpioi: gpio@48002000 {
89				compatible = "st,stm32-gpio";
90				gpio-controller;
91				#gpio-cells = <2>;
92				reg = <0x48002000 0x400>;
93				clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
94			};
95		};
96
97		usart3: serial@40004800 {
98			compatible = "st,stm32-usart", "st,stm32-uart";
99			reg = <0x40004800 0x400>;
100			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
101			resets = <&rctl STM32_RESET(APB1L, 18U)>;
102			interrupts = <39 0>;
103			status = "disabled";
104		};
105
106		uart4: serial@40004c00 {
107			compatible = "st,stm32-uart";
108			reg = <0x40004c00 0x400>;
109			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
110			resets = <&rctl STM32_RESET(APB1L, 19U)>;
111			interrupts = <52 0>;
112			status = "disabled";
113		};
114
115		uart5: serial@40005000 {
116			compatible = "st,stm32-uart";
117			reg = <0x40005000 0x400>;
118			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
119			resets = <&rctl STM32_RESET(APB1L, 20U)>;
120			interrupts = <53 0>;
121			status = "disabled";
122		};
123
124		i2c2: i2c@40005800 {
125			compatible = "st,stm32-i2c-v2";
126			clock-frequency = <I2C_BITRATE_STANDARD>;
127			#address-cells = <1>;
128			#size-cells = <0>;
129			reg = <0x40005800 0x400>;
130			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
131			interrupts = <33 0>, <34 0>;
132			interrupt-names = "event", "error";
133			status = "disabled";
134		};
135
136		i2c4: i2c@40008400 {
137			compatible = "st,stm32-i2c-v2";
138			clock-frequency = <I2C_BITRATE_STANDARD>;
139			#address-cells = <1>;
140			#size-cells = <0>;
141			reg = <0x40008400 0x400>;
142			clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
143			interrupts = <84 0>, <83 0>;
144			interrupt-names = "event", "error";
145			status = "disabled";
146		};
147
148		spi2: spi@40003800 {
149			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
150			#address-cells = <1>;
151			#size-cells = <0>;
152			reg = <0x40003800 0x400>;
153			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
154			interrupts = <36 5>;
155			status = "disabled";
156		};
157
158		spi3: spi@40003c00 {
159			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
160			#address-cells = <1>;
161			#size-cells = <0>;
162			reg = <0x40003c00 0x400>;
163			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
164			interrupts = <51 5>;
165			status = "disabled";
166		};
167
168		timers3: timers@40000400 {
169			compatible = "st,stm32-timers";
170			reg = <0x40000400 0x400>;
171			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
172			resets = <&rctl STM32_RESET(APB1L, 1U)>;
173			interrupts = <29 0>;
174			interrupt-names = "global";
175			st,prescaler = <0>;
176			status = "disabled";
177
178			pwm {
179				compatible = "st,stm32-pwm";
180				status = "disabled";
181				#pwm-cells = <3>;
182			};
183
184			counter {
185				compatible = "st,stm32-counter";
186				status = "disabled";
187			};
188		};
189
190		timers4: timers@40000800 {
191			compatible = "st,stm32-timers";
192			reg = <0x40000800 0x400>;
193			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
194			resets = <&rctl STM32_RESET(APB1L, 2U)>;
195			interrupts = <30 0>;
196			interrupt-names = "global";
197			st,prescaler = <0>;
198			status = "disabled";
199
200			pwm {
201				compatible = "st,stm32-pwm";
202				status = "disabled";
203				#pwm-cells = <3>;
204			};
205
206			counter {
207				compatible = "st,stm32-counter";
208				status = "disabled";
209			};
210		};
211
212		timers5: timers@40000c00 {
213			compatible = "st,stm32-timers";
214			reg = <0x40000c00 0x400>;
215			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
216			resets = <&rctl STM32_RESET(APB1L, 3U)>;
217			interrupts = <50 0>;
218			interrupt-names = "global";
219			st,prescaler = <0>;
220			status = "disabled";
221
222			pwm {
223				compatible = "st,stm32-pwm";
224				status = "disabled";
225				#pwm-cells = <3>;
226			};
227
228			counter {
229				compatible = "st,stm32-counter";
230				status = "disabled";
231			};
232		};
233
234		timers7: timers@40001400 {
235			compatible = "st,stm32-timers";
236			reg = <0x40001400 0x400>;
237			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
238			resets = <&rctl STM32_RESET(APB1L, 5U)>;
239			interrupts = <55 0>;
240			interrupt-names = "global";
241			st,prescaler = <0>;
242			status = "disabled";
243
244			pwm {
245				compatible = "st,stm32-pwm";
246				status = "disabled";
247				#pwm-cells = <3>;
248			};
249
250			counter {
251				compatible = "st,stm32-counter";
252				status = "disabled";
253			};
254		};
255
256		timers8: timers@40013400 {
257			compatible = "st,stm32-timers";
258			reg = <0x40013400 0x400>;
259			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
260			resets = <&rctl STM32_RESET(APB2, 13U)>;
261			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
262			interrupt-names = "brk", "up", "trgcom", "cc";
263			st,prescaler = <0>;
264			status = "disabled";
265
266			pwm {
267				compatible = "st,stm32-pwm";
268				status = "disabled";
269				#pwm-cells = <3>;
270			};
271		};
272
273		timers17: timers@40014800 {
274			compatible = "st,stm32-timers";
275			reg = <0x40014800 0x400>;
276			clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
277			resets = <&rctl STM32_RESET(APB2, 18U)>;
278			interrupts = <26 0>;
279			interrupt-names = "global";
280			st,prescaler = <0>;
281			status = "disabled";
282
283			pwm {
284				compatible = "st,stm32-pwm";
285				status = "disabled";
286				#pwm-cells = <3>;
287			};
288
289			counter {
290				compatible = "st,stm32-counter";
291				status = "disabled";
292			};
293		};
294
295		can1: can@40006400 {
296			compatible = "st,stm32-bxcan";
297			reg = <0x40006400 0x400>;
298			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
299			interrupt-names = "TX", "RX0", "RX1", "SCE";
300			clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN
301			status = "disabled";
302		};
303
304		usbotg_fs: otgfs@50000000 {
305			compatible = "st,stm32-otgfs";
306			reg = <0x50000000 0x40000>;
307			interrupts = <67 0>;
308			interrupt-names = "otgfs";
309			num-bidir-endpoints = <6>;
310			ram-size = <1280>;
311			maximum-speed = "full-speed";
312			clocks = <&rcc STM32_CLOCK(AHB2, 12U)>,
313				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
314			phys = <&otgfs_phy>;
315			status = "disabled";
316		};
317
318		dma1: dma@40020000 {
319			dma-offset = <0>;
320		};
321
322		dma2: dma@40020400 {
323			dma-offset = <7>;
324		};
325
326		dmamux1: dmamux@40020800 {
327			compatible = "st,stm32-dmamux";
328			#dma-cells = <3>;
329			reg = <0x40020800 0x400>;
330			interrupts = <94 0>;
331			clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
332			dma-channels = <14>;
333			dma-generators = <4>;
334			dma-requests= <89>;
335			status = "disabled";
336		};
337
338		sdmmc1: sdmmc@50062400 {
339			compatible = "st,stm32-sdmmc";
340			reg = <0x50062400 0x400>;
341			clocks = <&rcc STM32_CLOCK(AHB2, 22U)>,
342				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
343			resets = <&rctl STM32_RESET(AHB2, 22U)>;
344			interrupts = <49 0>;
345			status = "disabled";
346		};
347
348		sdmmc2: sdmmc@50062800 {
349			compatible = "st,stm32-sdmmc";
350			reg = <0x50062800 0x400>;
351			clocks = <&rcc STM32_CLOCK(AHB2, 23U)>,
352				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
353			resets = <&rctl STM32_RESET(AHB2, 23U)>;
354			interrupts = <47 0>;
355			status = "disabled";
356		};
357
358		dac1: dac@40007400 {
359			compatible = "st,stm32-dac";
360			reg = <0x40007400 0x400>;
361			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
362			status = "disabled";
363			#io-channel-cells = <1>;
364		};
365
366		octospi1: octospi@a0001000 {
367			compatible = "st,stm32-ospi";
368			reg = <0xa0001000 0x400>;
369			interrupts = <71 0>;
370			clock-names = "ospix", "ospi-ker", "ospi-mgr";
371			clocks = <&rcc STM32_CLOCK(AHB3, 8U)>,
372				<&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>,
373				<&rcc STM32_CLOCK(AHB2, 20U)>;
374
375			#address-cells = <1>;
376			#size-cells = <0>;
377			status = "disabled";
378		};
379
380		octospi2: octospi@a0001400 {
381			compatible = "st,stm32-ospi";
382			reg = <0xa0001400 0x400>;
383			interrupts = <76 0>;
384			clock-names = "ospix", "ospi-ker", "ospi-mgr";
385			clocks = <&rcc STM32_CLOCK(AHB3, 9U)>,
386				<&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>,
387				<&rcc STM32_CLOCK(AHB2, 20U)>;
388
389			#address-cells = <1>;
390			#size-cells = <0>;
391			status = "disabled";
392		};
393	};
394
395	otgfs_phy: otgfs_phy {
396		compatible = "usb-nop-xceiv";
397		#phy-cells = <0>;
398	};
399
400	smbus2: smbus2 {
401		compatible = "st,stm32-smbus";
402		#address-cells = <1>;
403		#size-cells = <0>;
404		i2c = <&i2c2>;
405		status = "disabled";
406	};
407
408	smbus4: smbus4 {
409		compatible = "st,stm32-smbus";
410		#address-cells = <1>;
411		#size-cells = <0>;
412		i2c = <&i2c4>;
413		status = "disabled";
414	};
415};
416