Lines Matching +full:stm32 +full:- +full:dma +full:- +full:v2
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/clock/stm32wb0_clock.h>
13 #include <zephyr/dt-bindings/reset/stm32wb0_reset.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
25 zephyr,flash-controller = &flash;
26 zephyr,bt-hci = &bt_hci_wb0;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 compatible = "arm,cortex-m0+";
41 compatible = "mmio-sram";
45 /* High-speed clock nodes
49 clk_hse: clk-hse {
50 #clock-cells = <0>;
51 compatible = "fixed-clock";
52 clock-frequency = <DT_FREQ_M(32)>;
56 clk_hsi: clk-hsi {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <DT_FREQ_M(64)>;
67 #clock-cells = <0>;
68 compatible = "fixed-clock";
69 clock-frequency = <DT_FREQ_M(64)>;
75 * 'slow-clock' property of the RCC node.
77 clk_lse: clk-lse {
78 #clock-cells = <0>;
79 compatible = "st,stm32-lse-clock";
80 clock-frequency = <32768>;
81 driving-capability = <1>;
85 clk_lsi: clk-lsi {
86 /* "fixed-clock" compatible is required for compatibility with the
89 #clock-cells = <0>;
90 compatible = "st,stm32wb0-lsi-clock", "fixed-clock";
91 clock-frequency = <DT_FREQ_K(32)>;
97 * are stopped, and cannot wake up the SoC, if this is selected as slow-clock!
99 clk_16mhz_div512: clk-16mhz-div512 {
100 #clock-cells = <0>;
101 compatible = "fixed-clock";
102 clock-frequency = <(DT_FREQ_M(16) / 512)>;
108 flash: flash-controller@40001000 {
109 compatible = "st,stm32wb0-flash-controller", "st,stm32-flash-controller";
113 #address-cells = <1>;
114 #size-cells = <1>;
117 compatible = "st,stm32-nv-flash", "soc-nv-flash";
118 write-block-size = <4>;
119 erase-block-size = <2048>;
121 max-erase-time = <40>;
126 compatible = "st,stm32wb0-rcc";
128 #clock-cells = <2>;
130 rctl: reset-controller {
131 compatible = "st,stm32-rcc-rctl";
132 #reset-cells = <1>;
137 compatible = "st,stm32wb0-pwr";
146 gpio_intc: interrupt-controller@40000000 {
147 compatible = "st,stm32wb0-gpio-intc";
148 interrupt-controller;
149 #interrupt-cells = <1>;
150 #address-cells = <1>;
152 num-lines = <32>;
154 interrupt-names = "gpioa", "gpiob";
155 line-ranges = <0 16>, <16 16>;
158 pinctrl: pin-controller@48000000 {
159 compatible = "st,stm32-pinctrl";
160 #address-cells = <1>;
161 #size-cells = <1>;
165 compatible = "st,stm32-gpio";
166 gpio-controller;
167 #gpio-cells = <2>;
173 compatible = "st,stm32-gpio";
174 gpio-controller;
175 #gpio-cells = <2>;
182 compatible = "st,stm32-usart", "st,stm32-uart";
192 compatible = "st,stm32-lpuart", "st,stm32-uart";
201 compatible = "st,stm32-i2c-v2";
202 clock-frequency = <I2C_BITRATE_STANDARD>;
203 #address-cells = <1>;
204 #size-cells = <0>;
208 interrupt-names = "combined";
213 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
214 #address-cells = <1>;
215 #size-cells = <0>;
223 compatible = "st,stm32wb0-adc";
228 * - first entry is digital part of ADC block (always-on)
229 * - second entry is analog part of ADC block (on-demand)
234 #io-channel-cells = <1>;
238 dma1: dma@48700000 {
239 compatible = "st,stm32-dma-v2bis";
240 #dma-cells = <2>;
244 dma-requests = <8>;
245 dma-offset = <0>;
250 compatible = "st,stm32-dmamux";
252 /* `clocks` property is identical between DMA and DMAMUX
256 #dma-cells = <3>;
257 dma-channels = <8>;
258 dma-generators = <1>;
259 dma-requests= <25>;
265 compatible = "st,hci-stm32wb0";
271 arm,num-irq-priority-bits = <2>;