1/* 2 * Copyright (c) 2021 The Chromium OS Authors 3 * Copyright (c) 2020 Linaro Limited 4 * Copyright (c) 2024 STMicroelectronics 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 10#include <arm/armv8-m.dtsi> 11#include <zephyr/dt-bindings/clock/stm32l4_clock.h> 12#include <zephyr/dt-bindings/gpio/gpio.h> 13#include <zephyr/dt-bindings/i2c/i2c.h> 14#include <zephyr/dt-bindings/pwm/pwm.h> 15#include <zephyr/dt-bindings/pwm/stm32_pwm.h> 16#include <zephyr/dt-bindings/dma/stm32_dma.h> 17#include <zephyr/dt-bindings/adc/stm32l4_adc.h> 18#include <zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h> 19#include <zephyr/dt-bindings/adc/adc.h> 20#include <zephyr/dt-bindings/flash_controller/ospi.h> 21#include <freq.h> 22 23/ { 24 chosen { 25 zephyr,entropy = &rng; 26 zephyr,flash-controller = &flash; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-m33"; 36 reg = <0>; 37 #address-cells = <1>; 38 #size-cells = <1>; 39 cpu-power-states = <&stop0 &stop1 &stop2>; 40 41 mpu: mpu@e000ed90 { 42 compatible = "arm,armv8m-mpu"; 43 reg = <0xe000ed90 0x40>; 44 }; 45 }; 46 47 power-states { 48 stop0: state0 { 49 compatible = "zephyr,power-state"; 50 power-state-name = "suspend-to-idle"; 51 substate-id = <1>; 52 min-residency-us = <100>; 53 }; 54 stop1: state1 { 55 compatible = "zephyr,power-state"; 56 power-state-name = "suspend-to-idle"; 57 substate-id = <2>; 58 min-residency-us = <500>; 59 }; 60 stop2: state2 { 61 compatible = "zephyr,power-state"; 62 power-state-name = "suspend-to-idle"; 63 substate-id = <3>; 64 min-residency-us = <900>; 65 }; 66 }; 67 }; 68 69 sram0: memory@20000000 { 70 compatible = "mmio-sram"; 71 }; 72 73 clocks { 74 clk_hse: clk-hse { 75 #clock-cells = <0>; 76 compatible = "st,stm32-hse-clock"; 77 status = "disabled"; 78 }; 79 80 clk_hsi: clk-hsi { 81 #clock-cells = <0>; 82 compatible = "fixed-clock"; 83 clock-frequency = <DT_FREQ_M(16)>; 84 status = "disabled"; 85 }; 86 87 clk_hsi48: clk-hsi48 { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <DT_FREQ_M(48)>; 91 status = "disabled"; 92 }; 93 94 clk_msi: clk-msi { 95 #clock-cells = <0>; 96 compatible = "st,stm32-msi-clock"; 97 msi-range = <6>; /* 4MHz (reset value) */ 98 status = "disabled"; 99 }; 100 101 clk_lse: clk-lse { 102 #clock-cells = <0>; 103 compatible = "st,stm32-lse-clock"; 104 clock-frequency = <32768>; 105 driving-capability = <0>; 106 status = "disabled"; 107 }; 108 109 clk_lsi: clk-lsi { 110 #clock-cells = <0>; 111 compatible = "fixed-clock"; 112 clock-frequency = <DT_FREQ_K(32)>; 113 status = "disabled"; 114 }; 115 116 pll: pll { 117 #clock-cells = <0>; 118 compatible = "st,stm32l4-pll-clock"; 119 status = "disabled"; 120 }; 121 }; 122 123 soc { 124 flash: flash-controller@40022000 { 125 compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller"; 126 reg = <0x40022000 0x400>; 127 interrupts = <6 0>; 128 clocks = <&rcc STM32_CLOCK(AHB1, 8U)>; 129 130 #address-cells = <1>; 131 #size-cells = <1>; 132 133 flash0: flash@8000000 { 134 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 135 write-block-size = <8>; 136 erase-block-size = <2048>; 137 138 /* using maximum erase time(ms) for 4K page, since 139 * datasheet does not show the maximum erase 140 * for a 2K(dual-bank) page. 141 */ 142 max-erase-time = <25>; 143 }; 144 }; 145 146 rcc: rcc@40021000 { 147 compatible = "st,stm32-rcc"; 148 clocks-controller; 149 #clock-cells = <2>; 150 reg = <0x40021000 0x400>; 151 undershoot-prevention; 152 153 rctl: reset-controller { 154 compatible = "st,stm32-rcc-rctl"; 155 #reset-cells = <1>; 156 }; 157 }; 158 159 exti: interrupt-controller@4000f400 { 160 compatible = "st,stm32g0-exti", "st,stm32-exti"; 161 interrupt-controller; 162 #interrupt-cells = <1>; 163 reg = <0x4000f400 0x400>; 164 num-lines = <16>; 165 interrupts = <11 0>, <12 0>, <13 0>, <14 0>, 166 <15 0>, <16 0>, <17 0>, <18 0>, 167 <19 0>, <20 0>, <21 0>, <22 0>, 168 <23 0>, <24 0>, <25 0>, <26 0>; 169 interrupt-names = "line0", "line1", "line2", "line3", 170 "line4", "line5", "line6", "line7", 171 "line8", "line9", "line10", "line11", 172 "line12", "line13", "line14", "line15"; 173 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 174 <4 1>, <5 1>, <6 1>, <7 1>, 175 <8 1>, <9 1>, <10 1>, <11 1>, 176 <12 1>, <13 1>, <14 1>, <15 1>; 177 }; 178 179 pinctrl: pin-controller@42020000 { 180 compatible = "st,stm32-pinctrl"; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 reg = <0x42020000 0x2000>; 184 185 gpioa: gpio@42020000 { 186 compatible = "st,stm32-gpio"; 187 gpio-controller; 188 #gpio-cells = <2>; 189 reg = <0x42020000 0x400>; 190 clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; 191 }; 192 193 gpiob: gpio@42020400 { 194 compatible = "st,stm32-gpio"; 195 gpio-controller; 196 #gpio-cells = <2>; 197 reg = <0x42020400 0x400>; 198 clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; 199 }; 200 201 gpioc: gpio@42020800 { 202 compatible = "st,stm32-gpio"; 203 gpio-controller; 204 #gpio-cells = <2>; 205 reg = <0x42020800 0x400>; 206 clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; 207 }; 208 209 gpiod: gpio@42020c00 { 210 compatible = "st,stm32-gpio"; 211 gpio-controller; 212 #gpio-cells = <2>; 213 reg = <0x42020c00 0x400>; 214 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>; 215 }; 216 217 gpioe: gpio@42021000 { 218 compatible = "st,stm32-gpio"; 219 gpio-controller; 220 #gpio-cells = <2>; 221 reg = <0x42021000 0x400>; 222 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; 223 }; 224 225 gpiof: gpio@42021400 { 226 compatible = "st,stm32-gpio"; 227 gpio-controller; 228 #gpio-cells = <2>; 229 reg = <0x42021400 0x400>; 230 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>; 231 }; 232 233 gpiog: gpio@42021800 { 234 compatible = "st,stm32-gpio"; 235 gpio-controller; 236 #gpio-cells = <2>; 237 reg = <0x42021800 0x400>; 238 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; 239 }; 240 241 gpioh: gpio@42021c00 { 242 compatible = "st,stm32-gpio"; 243 gpio-controller; 244 #gpio-cells = <2>; 245 reg = <0x42021c00 0x400>; 246 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; 247 }; 248 }; 249 250 iwdg: watchdog@40003000 { 251 compatible = "st,stm32-watchdog"; 252 reg = <0x40003000 0x400>; 253 status = "disabled"; 254 }; 255 256 wwdg: watchdog@40002c00 { 257 compatible = "st,stm32-window-watchdog"; 258 reg = <0x40002C00 0x400>; 259 clocks = <&rcc STM32_CLOCK(APB1, 11U)>; 260 interrupts = <0 6>; 261 status = "disabled"; 262 }; 263 264 usart1: serial@40013800 { 265 compatible = "st,stm32-usart", "st,stm32-uart"; 266 reg = <0x40013800 0x400>; 267 clocks = <&rcc STM32_CLOCK(APB2, 14U)>; 268 resets = <&rctl STM32_RESET(APB2, 14U)>; 269 interrupts = <61 0>; 270 status = "disabled"; 271 }; 272 273 usart2: serial@40004400 { 274 compatible = "st,stm32-usart", "st,stm32-uart"; 275 reg = <0x40004400 0x400>; 276 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 277 resets = <&rctl STM32_RESET(APB1L, 17U)>; 278 interrupts = <62 0>; 279 status = "disabled"; 280 }; 281 282 usart3: serial@40004800 { 283 compatible = "st,stm32-usart", "st,stm32-uart"; 284 reg = <0x40004800 0x400>; 285 clocks = <&rcc STM32_CLOCK(APB1, 18U)>; 286 resets = <&rctl STM32_RESET(APB1L, 18U)>; 287 interrupts = <63 0>; 288 status = "disabled"; 289 }; 290 291 uart4: serial@40004c00 { 292 compatible = "st,stm32-uart"; 293 reg = <0x40004c00 0x400>; 294 clocks = <&rcc STM32_CLOCK(APB1, 19U)>; 295 resets = <&rctl STM32_RESET(APB1L, 19U)>; 296 interrupts = <64 0>; 297 status = "disabled"; 298 }; 299 300 uart5: serial@40005000 { 301 compatible = "st,stm32-uart"; 302 reg = <0x40005000 0x400>; 303 clocks = <&rcc STM32_CLOCK(APB1, 20U)>; 304 resets = <&rctl STM32_RESET(APB1L, 20U)>; 305 interrupts = <65 0>; 306 status = "disabled"; 307 }; 308 309 lpuart1: serial@40008000 { 310 compatible = "st,stm32-lpuart", "st,stm32-uart"; 311 reg = <0x40008000 0x400>; 312 clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>; 313 resets = <&rctl STM32_RESET(APB1H, 0U)>; 314 interrupts = <66 0>; 315 status = "disabled"; 316 }; 317 318 lptim1: timers@40007c00 { 319 compatible = "st,stm32-lptim"; 320 clocks = <&rcc STM32_CLOCK(APB1, 31U)>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 reg = <0x40007c00 0x400>; 324 interrupts = <67 1>; 325 interrupt-names = "wakeup"; 326 status = "disabled"; 327 }; 328 329 dma1: dma@40020000 { 330 compatible = "st,stm32-dma-v2"; 331 #dma-cells = <3>; 332 reg = <0x40020000 0x400>; 333 interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0>; 334 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; 335 dma-requests = <8>; 336 dma-offset = <0>; 337 status = "disabled"; 338 }; 339 340 dma2: dma@40020400 { 341 compatible = "st,stm32-dma-v2"; 342 #dma-cells = <3>; 343 reg = <0x40020400 0x400>; 344 interrupts = <80 0 81 0 82 0 83 0 84 0 85 0 86 0 87 0>; 345 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; 346 dma-requests = <8>; 347 dma-offset = <8>; 348 status = "disabled"; 349 }; 350 351 dmamux1: dmamux@40020800 { 352 compatible = "st,stm32-dmamux"; 353 #dma-cells = <3>; 354 reg = <0x40020800 0x400>; 355 interrupts = <27 0>; 356 clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; 357 dma-channels = <16>; 358 dma-generators = <4>; 359 dma-requests= <90>; 360 status = "disabled"; 361 }; 362 363 i2c1: i2c@40005400 { 364 compatible = "st,stm32-i2c-v2"; 365 clock-frequency = <I2C_BITRATE_STANDARD>; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 reg = <0x40005400 0x400>; 369 clocks = <&rcc STM32_CLOCK(APB1, 21U)>; 370 interrupts = <55 0>, <56 0>; 371 interrupt-names = "event", "error"; 372 status = "disabled"; 373 }; 374 375 i2c2: i2c@40005800 { 376 compatible = "st,stm32-i2c-v2"; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 clock-frequency = <I2C_BITRATE_STANDARD>; 380 reg = <0x40005800 0x400>; 381 clocks = <&rcc STM32_CLOCK(APB1, 22U)>; 382 interrupts = <57 0>, <58 0>; 383 interrupt-names = "event", "error"; 384 status = "disabled"; 385 }; 386 387 spi1: spi@40013000 { 388 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 reg = <0x40013000 0x400>; 392 interrupts = <59 5>; 393 clocks = <&rcc STM32_CLOCK(APB2, 12U)>; 394 status = "disabled"; 395 }; 396 397 sdmmc1: sdmmc@420c8000 { 398 compatible = "st,stm32-sdmmc"; 399 reg = <0x420c8000 0x400>; 400 clocks = <&rcc STM32_CLOCK(AHB2, 22U)>, 401 <&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>; 402 resets = <&rctl STM32_RESET(AHB2, 22U)>; 403 interrupts = <78 0>; 404 status = "disabled"; 405 }; 406 407 dac1: dac@40007400 { 408 compatible = "st,stm32-dac"; 409 reg = <0x40007400 0x400>; 410 clocks = <&rcc STM32_CLOCK(APB1, 29U)>; 411 status = "disabled"; 412 #io-channel-cells = <1>; 413 }; 414 415 spi2: spi@40003800 { 416 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 reg = <0x40003800 0x400>; 420 interrupts = <60 5>; 421 clocks = <&rcc STM32_CLOCK(APB1, 14U)>; 422 status = "disabled"; 423 }; 424 425 spi3: spi@40003c00 { 426 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 reg = <0x40003c00 0x400>; 430 interrupts = <99 5>; 431 clocks = <&rcc STM32_CLOCK(APB1, 15U)>; 432 status = "disabled"; 433 }; 434 435 octospi1: octospi@44021000 { 436 compatible = "st,stm32-ospi"; 437 reg = <0x44021000 0x400>; 438 interrupts = <76 0>; 439 clock-names = "ospix", "ospi-ker"; 440 clocks = <&rcc STM32_CLOCK(AHB3, 8U)>, 441 <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 status = "disabled"; 445 }; 446 447 rng: rng@420c0800 { 448 compatible = "st,stm32-rng"; 449 reg = <0x420c0800 0x400>; 450 interrupts = <94 0>; 451 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>; 452 nist-config = <0xf00d00>; 453 health-test-magic = <0x17590abc>; 454 health-test-config = <0xa2b3>; 455 status = "disabled"; 456 }; 457 458 rtc: rtc@40002800 { 459 compatible = "st,stm32-rtc"; 460 reg = <0x40002800 0x400>; 461 interrupts = <2 0>; 462 clocks = <&rcc STM32_CLOCK(APB1, 10U)>; 463 prescaler = <32768>; 464 alarms-count = <2>; 465 alrm-exti-line = <17>; 466 status = "disabled"; 467 }; 468 469 timers1: timers@40012c00 { 470 compatible = "st,stm32-timers"; 471 reg = <0x40012c00 0x400>; 472 clocks = <&rcc STM32_CLOCK(APB2, 11U)>; 473 resets = <&rctl STM32_RESET(APB2, 11U)>; 474 interrupts = <41 0>, <42 0>, <43 0>, <44 0>; 475 interrupt-names = "brk", "up", "trgcom", "cc"; 476 st,prescaler = <0>; 477 status = "disabled"; 478 479 pwm { 480 compatible = "st,stm32-pwm"; 481 status = "disabled"; 482 #pwm-cells = <3>; 483 }; 484 }; 485 486 timers2: timers@40000000 { 487 compatible = "st,stm32-timers"; 488 reg = <0x40000000 0x400>; 489 clocks = <&rcc STM32_CLOCK(APB1, 0U)>; 490 resets = <&rctl STM32_RESET(APB1L, 0U)>; 491 interrupts = <45 0>; 492 interrupt-names = "global"; 493 st,prescaler = <0>; 494 status = "disabled"; 495 496 pwm { 497 compatible = "st,stm32-pwm"; 498 status = "disabled"; 499 #pwm-cells = <3>; 500 }; 501 502 counter { 503 compatible = "st,stm32-counter"; 504 status = "disabled"; 505 }; 506 }; 507 508 timers3: timers@40000400 { 509 compatible = "st,stm32-timers"; 510 reg = <0x40000400 0x400>; 511 clocks = <&rcc STM32_CLOCK(APB1, 1U)>; 512 resets = <&rctl STM32_RESET(APB1L, 1U)>; 513 interrupts = <46 0>; 514 interrupt-names = "global"; 515 st,prescaler = <0>; 516 status = "disabled"; 517 518 pwm { 519 compatible = "st,stm32-pwm"; 520 status = "disabled"; 521 #pwm-cells = <3>; 522 }; 523 524 counter { 525 compatible = "st,stm32-counter"; 526 status = "disabled"; 527 }; 528 }; 529 530 timers4: timers@40000800 { 531 compatible = "st,stm32-timers"; 532 reg = <0x40000800 0x400>; 533 clocks = <&rcc STM32_CLOCK(APB1, 2U)>; 534 resets = <&rctl STM32_RESET(APB1L, 2U)>; 535 interrupts = <47 0>; 536 interrupt-names = "global"; 537 st,prescaler = <0>; 538 status = "disabled"; 539 540 pwm { 541 compatible = "st,stm32-pwm"; 542 status = "disabled"; 543 #pwm-cells = <3>; 544 }; 545 546 counter { 547 compatible = "st,stm32-counter"; 548 status = "disabled"; 549 }; 550 }; 551 552 timers5: timers@40000c00 { 553 compatible = "st,stm32-timers"; 554 reg = <0x40000c00 0x400>; 555 clocks = <&rcc STM32_CLOCK(APB1, 3U)>; 556 resets = <&rctl STM32_RESET(APB1L, 3U)>; 557 interrupts = <48 0>; 558 interrupt-names = "global"; 559 st,prescaler = <0>; 560 status = "disabled"; 561 562 pwm { 563 compatible = "st,stm32-pwm"; 564 status = "disabled"; 565 #pwm-cells = <3>; 566 }; 567 568 counter { 569 compatible = "st,stm32-counter"; 570 status = "disabled"; 571 }; 572 }; 573 574 timers8: timers@40013400 { 575 compatible = "st,stm32-timers"; 576 reg = <0x40013400 0x400>; 577 clocks = <&rcc STM32_CLOCK(APB2, 13U)>; 578 resets = <&rctl STM32_RESET(APB2, 13U)>; 579 interrupts = <51 0>, <52 0>, <53 0>, <54 0>; 580 interrupt-names = "brk", "up", "trgcom", "cc"; 581 st,prescaler = <0>; 582 status = "disabled"; 583 584 pwm { 585 compatible = "st,stm32-pwm"; 586 status = "disabled"; 587 #pwm-cells = <3>; 588 }; 589 }; 590 591 timers15: timers@40014000 { 592 compatible = "st,stm32-timers"; 593 reg = <0x40014000 0x400>; 594 clocks = <&rcc STM32_CLOCK(APB2, 16U)>; 595 resets = <&rctl STM32_RESET(APB2, 16U)>; 596 interrupts = <69 0>; 597 interrupt-names = "global"; 598 st,prescaler = <0>; 599 status = "disabled"; 600 601 pwm { 602 compatible = "st,stm32-pwm"; 603 status = "disabled"; 604 #pwm-cells = <3>; 605 }; 606 607 counter { 608 compatible = "st,stm32-counter"; 609 status = "disabled"; 610 }; 611 }; 612 613 timers16: timers@40014400 { 614 compatible = "st,stm32-timers"; 615 reg = <0x40014400 0x400>; 616 clocks = <&rcc STM32_CLOCK(APB2, 17U)>; 617 resets = <&rctl STM32_RESET(APB2, 17U)>; 618 interrupts = <70 0>; 619 interrupt-names = "global"; 620 st,prescaler = <0>; 621 status = "disabled"; 622 623 pwm { 624 compatible = "st,stm32-pwm"; 625 status = "disabled"; 626 #pwm-cells = <3>; 627 }; 628 629 counter { 630 compatible = "st,stm32-counter"; 631 status = "disabled"; 632 }; 633 }; 634 635 timers17: timers@40014800 { 636 compatible = "st,stm32-timers"; 637 reg = <0x40014800 0x400>; 638 clocks = <&rcc STM32_CLOCK(APB2, 18U)>; 639 resets = <&rctl STM32_RESET(APB2, 18U)>; 640 interrupts = <71 0>; 641 interrupt-names = "global"; 642 st,prescaler = <0>; 643 status = "disabled"; 644 645 pwm { 646 compatible = "st,stm32-pwm"; 647 status = "disabled"; 648 #pwm-cells = <3>; 649 }; 650 651 counter { 652 compatible = "st,stm32-counter"; 653 status = "disabled"; 654 }; 655 }; 656 657 adc1: adc@42028000 { 658 compatible = "st,stm32-adc"; 659 reg = <0x42028000 0x100>; 660 clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; 661 interrupts = <37 0>; 662 status = "disabled"; 663 #io-channel-cells = <1>; 664 resolutions = <STM32_ADC_RES(12, 0x00) 665 STM32_ADC_RES(10, 0x01) 666 STM32_ADC_RES(8, 0x02) 667 STM32_ADC_RES(6, 0x03)>; 668 sampling-times = <3 7 13 25 48 93 248 641>; 669 st,adc-sequencer = "FULLY_CONFIGURABLE"; 670 st,adc-oversampler = "OVERSAMPLER_MINIMAL"; 671 }; 672 673 adc2: adc@42028100 { 674 compatible = "st,stm32-adc"; 675 reg = <0x42028100 0x100>; 676 clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; 677 interrupts = <37 0>; 678 status = "disabled"; 679 #io-channel-cells = <1>; 680 resolutions = <STM32_ADC_RES(12, 0x00) 681 STM32_ADC_RES(10, 0x01) 682 STM32_ADC_RES(8, 0x02) 683 STM32_ADC_RES(6, 0x03)>; 684 sampling-times = <3 7 13 25 48 93 248 641>; 685 st,adc-sequencer = "FULLY_CONFIGURABLE"; 686 st,adc-oversampler = "OVERSAMPLER_MINIMAL"; 687 }; 688 689 usb: usb@4000d400 { 690 compatible = "st,stm32-usb"; 691 reg = <0x4000d400 0x400>; 692 interrupts = <73 0>; 693 interrupt-names = "usb"; 694 num-bidir-endpoints = <8>; 695 ram-size = <1024>; 696 status = "disabled"; 697 clocks = <&rcc STM32_CLOCK(APB1_2, 21U)>, 698 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; 699 phys = <&usb_fs_phy>; 700 }; 701 702 ucpd1: ucpd@4000dc00 { 703 compatible = "st,stm32-ucpd"; 704 reg = <0x4000dc00 0x400>; 705 clocks = <&rcc STM32_CLOCK(APB1, 23U)>; 706 interrupts = <106 0>; 707 status = "disabled"; 708 }; 709 710 fmc: fmc@44020000 { 711 compatible = "st,stm32-fmc"; 712 reg = <0x44020000 0x400>; 713 clocks = <&rcc STM32_CLOCK(AHB3, 0U)>; 714 status = "disabled"; 715 }; 716 }; 717 718 die_temp: dietemp { 719 compatible = "st,stm32-temp-cal"; 720 ts-cal1-addr = <0x0BFA05A8>; 721 ts-cal2-addr = <0x0BFA05CA>; 722 ts-cal1-temp = <30>; 723 ts-cal2-temp = <130>; 724 ts-cal-vrefanalog = <3000>; 725 io-channels = <&adc1 17>; 726 status = "disabled"; 727 }; 728 729 vref: vref { 730 compatible = "st,stm32-vref"; 731 vrefint-cal-addr = <0x0BFA05AA>; 732 vrefint-cal-mv = <3000>; 733 io-channels = <&adc1 0>; 734 status = "disabled"; 735 }; 736 737 vbat: vbat { 738 compatible = "st,stm32-vbat"; 739 ratio = <3>; 740 io-channels = <&adc1 18>; 741 status = "disabled"; 742 }; 743 744 usb_fs_phy: usbphy { 745 compatible = "usb-nop-xceiv"; 746 #phy-cells = <0>; 747 }; 748 749 smbus1: smbus1 { 750 compatible = "st,stm32-smbus"; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 i2c = <&i2c1>; 754 status = "disabled"; 755 }; 756 757 smbus2: smbus2 { 758 compatible = "st,stm32-smbus"; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 i2c = <&i2c2>; 762 status = "disabled"; 763 }; 764 765}; 766 767&nvic { 768 arm,num-irq-priority-bits = <3>; 769}; 770
