1/* 2 * Copyright (c) 2021 The Chromium OS Authors 3 * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com> 4 * Copyright (c) 2024 STMicroelectronics 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 10#include <arm/armv7-m.dtsi> 11#include <zephyr/dt-bindings/clock/stm32g4_clock.h> 12#include <zephyr/dt-bindings/i2c/i2c.h> 13#include <zephyr/dt-bindings/gpio/gpio.h> 14#include <zephyr/dt-bindings/pwm/pwm.h> 15#include <zephyr/dt-bindings/adc/adc.h> 16#include <zephyr/dt-bindings/pwm/stm32_pwm.h> 17#include <zephyr/dt-bindings/dma/stm32_dma.h> 18#include <zephyr/dt-bindings/adc/stm32l4_adc.h> 19#include <zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h> 20#include <freq.h> 21 22/ { 23 chosen { 24 zephyr,entropy = &rng; 25 zephyr,flash-controller = &flash; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-m4f"; 35 reg = <0>; 36 cpu-power-states = <&stop0 &stop1>; 37 }; 38 39 power-states { 40 stop0: state0 { 41 compatible = "zephyr,power-state"; 42 power-state-name = "suspend-to-idle"; 43 substate-id = <1>; 44 min-residency-us = <20>; 45 }; 46 stop1: state1 { 47 compatible = "zephyr,power-state"; 48 power-state-name = "suspend-to-idle"; 49 substate-id = <2>; 50 min-residency-us = <100>; 51 }; 52 }; 53 }; 54 55 sram0: memory@20000000 { 56 compatible = "mmio-sram"; 57 }; 58 59 clocks { 60 clk_hse: clk-hse { 61 #clock-cells = <0>; 62 compatible = "st,stm32-hse-clock"; 63 status = "disabled"; 64 }; 65 66 clk_hsi: clk-hsi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <DT_FREQ_M(16)>; 70 status = "disabled"; 71 }; 72 73 clk_hsi48: clk-hsi48 { 74 #clock-cells = <0>; 75 compatible = "fixed-clock"; 76 clock-frequency = <DT_FREQ_M(48)>; 77 status = "disabled"; 78 }; 79 80 clk_lse: clk-lse { 81 #clock-cells = <0>; 82 compatible = "st,stm32-lse-clock"; 83 clock-frequency = <32768>; 84 driving-capability = <0>; 85 status = "disabled"; 86 }; 87 88 clk_lsi: clk-lsi { 89 #clock-cells = <0>; 90 compatible = "fixed-clock"; 91 clock-frequency = <DT_FREQ_K(32)>; 92 status = "disabled"; 93 }; 94 95 pll: pll { 96 #clock-cells = <0>; 97 compatible = "st,stm32g4-pll-clock"; 98 status = "disabled"; 99 }; 100 }; 101 102 soc { 103 /* 104 * Both adc instances cannot be used in parallel right now. 105 */ 106 adc1: adc@50000000 { 107 compatible = "st,stm32-adc"; 108 reg = <0x50000000 0x100>; 109 clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; 110 interrupts = <18 0>; 111 status = "disabled"; 112 #io-channel-cells = <1>; 113 resolutions = <STM32_ADC_RES(12, 0x00) 114 STM32_ADC_RES(10, 0x01) 115 STM32_ADC_RES(8, 0x02) 116 STM32_ADC_RES(6, 0x03)>; 117 sampling-times = <3 7 13 25 48 93 248 641>; 118 st,adc-sequencer = "FULLY_CONFIGURABLE"; 119 st,adc-oversampler = "OVERSAMPLER_MINIMAL"; 120 }; 121 122 adc2: adc@50000100 { 123 compatible = "st,stm32-adc"; 124 reg = <0x50000100 0x100>; 125 clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; 126 interrupts = <18 0>; 127 status = "disabled"; 128 #io-channel-cells = <1>; 129 resolutions = <STM32_ADC_RES(12, 0x00) 130 STM32_ADC_RES(10, 0x01) 131 STM32_ADC_RES(8, 0x02) 132 STM32_ADC_RES(6, 0x03)>; 133 sampling-times = <3 7 13 25 48 93 248 641>; 134 st,adc-sequencer = "FULLY_CONFIGURABLE"; 135 st,adc-oversampler = "OVERSAMPLER_MINIMAL"; 136 }; 137 138 dac1: dac@50000800 { 139 compatible = "st,stm32-dac"; 140 reg = <0x50000800 0x400>; 141 clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; 142 status = "disabled"; 143 #io-channel-cells = <1>; 144 }; 145 146 dac3: dac@50001000 { 147 compatible = "st,stm32-dac"; 148 reg = <0x50001000 0x400>; 149 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>; 150 status = "disabled"; 151 #io-channel-cells = <1>; 152 }; 153 154 flash: flash-controller@40022000 { 155 compatible = "st,stm32-flash-controller", "st,stm32g4-flash-controller"; 156 reg = <0x40022000 0x400>; 157 interrupts = <3 0>; 158 clocks = <&rcc STM32_CLOCK(AHB1, 8U)>; 159 160 #address-cells = <1>; 161 #size-cells = <1>; 162 163 flash0: flash@8000000 { 164 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 165 166 write-block-size = <8>; 167 erase-block-size = <2048>; 168 /* maximum erase time(ms) for a 2K sector */ 169 max-erase-time = <25>; 170 }; 171 }; 172 173 rcc: rcc@40021000 { 174 compatible = "st,stm32-rcc"; 175 #clock-cells = <2>; 176 reg = <0x40021000 0x400>; 177 undershoot-prevention; 178 179 rctl: reset-controller { 180 compatible = "st,stm32-rcc-rctl"; 181 #reset-cells = <1>; 182 }; 183 }; 184 185 exti: interrupt-controller@40010400 { 186 compatible = "st,stm32-exti"; 187 interrupt-controller; 188 #interrupt-cells = <1>; 189 #address-cells = <1>; 190 reg = <0x40010400 0x400>; 191 num-lines = <16>; 192 interrupts = <6 0>, <7 0>, <8 0>, <9 0>, 193 <10 0>, <23 0>, <40 0>; 194 interrupt-names = "line0", "line1", "line2-TSC", "line3", 195 "line4", "line5-9", "line10-15"; 196 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 197 <4 1>, <5 5>, <10 6>; 198 }; 199 200 pinctrl: pin-controller@48000000 { 201 compatible = "st,stm32-pinctrl"; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 reg = <0x48000000 0x2000>; 205 206 gpioa: gpio@48000000 { 207 compatible = "st,stm32-gpio"; 208 gpio-controller; 209 #gpio-cells = <2>; 210 reg = <0x48000000 0x400>; 211 clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; 212 }; 213 214 gpiob: gpio@48000400 { 215 compatible = "st,stm32-gpio"; 216 gpio-controller; 217 #gpio-cells = <2>; 218 reg = <0x48000400 0x400>; 219 clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; 220 }; 221 222 gpioc: gpio@48000800 { 223 compatible = "st,stm32-gpio"; 224 gpio-controller; 225 #gpio-cells = <2>; 226 reg = <0x48000800 0x400>; 227 clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; 228 }; 229 230 gpiod: gpio@48000c00 { 231 compatible = "st,stm32-gpio"; 232 gpio-controller; 233 #gpio-cells = <2>; 234 reg = <0x48000c00 0x400>; 235 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>; 236 }; 237 238 gpioe: gpio@48001000 { 239 compatible = "st,stm32-gpio"; 240 gpio-controller; 241 #gpio-cells = <2>; 242 reg = <0x48001000 0x400>; 243 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; 244 }; 245 246 gpiof: gpio@48001400 { 247 compatible = "st,stm32-gpio"; 248 gpio-controller; 249 #gpio-cells = <2>; 250 reg = <0x48001400 0x400>; 251 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>; 252 }; 253 254 gpiog: gpio@48001800 { 255 compatible = "st,stm32-gpio"; 256 gpio-controller; 257 #gpio-cells = <2>; 258 reg = <0x48001800 0x400>; 259 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; 260 }; 261 }; 262 263 usart1: serial@40013800 { 264 compatible = "st,stm32-usart", "st,stm32-uart"; 265 reg = <0x40013800 0x400>; 266 clocks = <&rcc STM32_CLOCK(APB2, 14U)>; 267 resets = <&rctl STM32_RESET(APB2, 14U)>; 268 interrupts = <37 0>; 269 status = "disabled"; 270 }; 271 272 usart2: serial@40004400 { 273 compatible = "st,stm32-usart", "st,stm32-uart"; 274 reg = <0x40004400 0x400>; 275 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 276 resets = <&rctl STM32_RESET(APB1L, 17U)>; 277 interrupts = <38 0>; 278 status = "disabled"; 279 }; 280 281 usart3: serial@40004800 { 282 compatible = "st,stm32-usart", "st,stm32-uart"; 283 reg = <0x40004800 0x400>; 284 clocks = <&rcc STM32_CLOCK(APB1, 18U)>; 285 resets = <&rctl STM32_RESET(APB1L, 18U)>; 286 interrupts = <39 0>; 287 status = "disabled"; 288 }; 289 290 uart4: serial@40004c00 { 291 compatible = "st,stm32-uart"; 292 reg = <0x40004c00 0x400>; 293 clocks = <&rcc STM32_CLOCK(APB1, 19U)>; 294 resets = <&rctl STM32_RESET(APB1L, 19U)>; 295 interrupts = <52 0>; 296 status = "disabled"; 297 }; 298 299 lpuart1: serial@40008000 { 300 compatible = "st,stm32-lpuart", "st,stm32-uart"; 301 reg = <0x40008000 0x400>; 302 clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>; 303 resets = <&rctl STM32_RESET(APB1H, 0U)>; 304 interrupts = <91 0>; 305 status = "disabled"; 306 }; 307 308 iwdg: watchdog@40003000 { 309 compatible = "st,stm32-watchdog"; 310 reg = <0x40003000 0x400>; 311 status = "disabled"; 312 }; 313 314 wwdg: watchdog@40002c00 { 315 compatible = "st,stm32-window-watchdog"; 316 reg = <0x40002C00 0x400>; 317 clocks = <&rcc STM32_CLOCK(APB1, 11U)>; 318 interrupts = <0 7>; 319 status = "disabled"; 320 }; 321 322 i2c1: i2c@40005400 { 323 compatible = "st,stm32-i2c-v2"; 324 clock-frequency = <I2C_BITRATE_STANDARD>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 reg = <0x40005400 0x400>; 328 clocks = <&rcc STM32_CLOCK(APB1, 21U)>; 329 interrupts = <31 0>, <32 0>; 330 interrupt-names = "event", "error"; 331 status = "disabled"; 332 }; 333 334 i2c2: i2c@40005800 { 335 compatible = "st,stm32-i2c-v2"; 336 clock-frequency = <I2C_BITRATE_STANDARD>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 reg = <0x40005800 0x400>; 340 clocks = <&rcc STM32_CLOCK(APB1, 22U)>; 341 interrupts = <33 0>, <34 0>; 342 interrupt-names = "event", "error"; 343 status = "disabled"; 344 }; 345 346 i2c3: i2c@40007800 { 347 compatible = "st,stm32-i2c-v2"; 348 clock-frequency = <I2C_BITRATE_STANDARD>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 reg = <0x40007800 0x400>; 352 clocks = <&rcc STM32_CLOCK(APB1, 30U)>; 353 interrupts = <92 0>, <93 0>; 354 interrupt-names = "event", "error"; 355 status = "disabled"; 356 }; 357 358 spi1: spi@40013000 { 359 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 reg = <0x40013000 0x400>; 363 interrupts = <35 5>; 364 clocks = <&rcc STM32_CLOCK(APB2, 12U)>; 365 status = "disabled"; 366 }; 367 368 spi2: spi@40003800 { 369 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 reg = <0x40003800 0x400>; 373 clocks = <&rcc STM32_CLOCK(APB1, 14U)>; 374 interrupts = <36 5>; 375 status = "disabled"; 376 }; 377 378 spi3: spi@40003c00 { 379 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 reg = <0x40003c00 0x400>; 383 clocks = <&rcc STM32_CLOCK(APB1, 15U)>; 384 interrupts = <51 5>; 385 status = "disabled"; 386 }; 387 388 fdcan1: can@40006400 { 389 compatible = "st,stm32-fdcan"; 390 reg = <0x40006400 0x400>, <0x4000a400 0x350>; 391 reg-names = "m_can", "message_ram"; 392 interrupts = <21 0>, <22 0>; 393 interrupt-names = "int0", "int1"; 394 clocks = <&rcc STM32_CLOCK(APB1, 25U)>; 395 bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; 396 status = "disabled"; 397 }; 398 399 lptim1: timers@40007c00 { 400 compatible = "st,stm32-lptim"; 401 clocks = <&rcc STM32_CLOCK(APB1, 31U)>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 reg = <0x40007c00 0x400>; 405 interrupts = <49 1>; 406 interrupt-names = "wakeup"; 407 status = "disabled"; 408 }; 409 410 timers1: timers@40012c00 { 411 compatible = "st,stm32-timers"; 412 reg = <0x40012c00 0x400>; 413 clocks = <&rcc STM32_CLOCK(APB2, 11U)>; 414 resets = <&rctl STM32_RESET(APB2, 11U)>; 415 interrupts = <24 0>, <25 0>, <26 0>, <27 0>; 416 interrupt-names = "brk", "up", "trgcom", "cc"; 417 st,prescaler = <0>; 418 status = "disabled"; 419 420 pwm { 421 compatible = "st,stm32-pwm"; 422 status = "disabled"; 423 #pwm-cells = <3>; 424 }; 425 }; 426 427 timers2: timers@40000000 { 428 compatible = "st,stm32-timers"; 429 reg = <0x40000000 0x400>; 430 clocks = <&rcc STM32_CLOCK(APB1, 0U)>; 431 resets = <&rctl STM32_RESET(APB1L, 0U)>; 432 interrupts = <28 0>; 433 interrupt-names = "global"; 434 st,prescaler = <0>; 435 status = "disabled"; 436 437 counter { 438 compatible = "st,stm32-counter"; 439 status = "disabled"; 440 }; 441 442 pwm { 443 compatible = "st,stm32-pwm"; 444 status = "disabled"; 445 #pwm-cells = <3>; 446 }; 447 }; 448 449 timers3: timers@40000400 { 450 compatible = "st,stm32-timers"; 451 reg = <0x40000400 0x400>; 452 clocks = <&rcc STM32_CLOCK(APB1, 1U)>; 453 resets = <&rctl STM32_RESET(APB1L, 1U)>; 454 interrupts = <29 0>; 455 interrupt-names = "global"; 456 st,prescaler = <0>; 457 status = "disabled"; 458 459 counter { 460 compatible = "st,stm32-counter"; 461 status = "disabled"; 462 }; 463 464 pwm { 465 compatible = "st,stm32-pwm"; 466 status = "disabled"; 467 #pwm-cells = <3>; 468 }; 469 }; 470 471 timers4: timers@40000800 { 472 compatible = "st,stm32-timers"; 473 reg = <0x40000800 0x400>; 474 clocks = <&rcc STM32_CLOCK(APB1, 2U)>; 475 resets = <&rctl STM32_RESET(APB1L, 2U)>; 476 interrupts = <30 0>; 477 interrupt-names = "global"; 478 st,prescaler = <0>; 479 status = "disabled"; 480 481 counter { 482 compatible = "st,stm32-counter"; 483 status = "disabled"; 484 }; 485 486 pwm { 487 compatible = "st,stm32-pwm"; 488 status = "disabled"; 489 #pwm-cells = <3>; 490 }; 491 }; 492 493 timers6: timers@40001000 { 494 compatible = "st,stm32-timers"; 495 reg = <0x40001000 0x400>; 496 clocks = <&rcc STM32_CLOCK(APB1, 4U)>; 497 resets = <&rctl STM32_RESET(APB1L, 4U)>; 498 interrupts = <54 0>; 499 interrupt-names = "global"; 500 st,prescaler = <0>; 501 status = "disabled"; 502 }; 503 504 timers7: timers@40001400 { 505 compatible = "st,stm32-timers"; 506 reg = <0x40001400 0x400>; 507 clocks = <&rcc STM32_CLOCK(APB1, 5U)>; 508 resets = <&rctl STM32_RESET(APB1L, 5U)>; 509 interrupts = <55 0>; 510 interrupt-names = "global"; 511 st,prescaler = <0>; 512 status = "disabled"; 513 }; 514 515 timers8: timers@40013400 { 516 compatible = "st,stm32-timers"; 517 reg = <0x40013400 0x400>; 518 clocks = <&rcc STM32_CLOCK(APB2, 13U)>; 519 resets = <&rctl STM32_RESET(APB2, 13U)>; 520 interrupts = <43 0>, <44 0>, <45 0>, <46 0>; 521 interrupt-names = "brk", "up", "trgcom", "cc"; 522 st,prescaler = <0>; 523 status = "disabled"; 524 525 pwm { 526 compatible = "st,stm32-pwm"; 527 status = "disabled"; 528 #pwm-cells = <3>; 529 }; 530 }; 531 532 timers15: timers@40014000 { 533 compatible = "st,stm32-timers"; 534 reg = <0x40014000 0x400>; 535 clocks = <&rcc STM32_CLOCK(APB2, 16U)>; 536 resets = <&rctl STM32_RESET(APB2, 16U)>; 537 interrupts = <24 0>; 538 interrupt-names = "global"; 539 st,prescaler = <0>; 540 status = "disabled"; 541 542 pwm { 543 compatible = "st,stm32-pwm"; 544 status = "disabled"; 545 #pwm-cells = <3>; 546 }; 547 548 counter { 549 compatible = "st,stm32-counter"; 550 status = "disabled"; 551 }; 552 }; 553 554 timers16: timers@40014400 { 555 compatible = "st,stm32-timers"; 556 reg = <0x40014400 0x400>; 557 clocks = <&rcc STM32_CLOCK(APB2, 17U)>; 558 resets = <&rctl STM32_RESET(APB2, 17U)>; 559 interrupts = <25 0>; 560 interrupt-names = "global"; 561 st,prescaler = <0>; 562 status = "disabled"; 563 564 pwm { 565 compatible = "st,stm32-pwm"; 566 status = "disabled"; 567 #pwm-cells = <3>; 568 }; 569 570 counter { 571 compatible = "st,stm32-counter"; 572 status = "disabled"; 573 }; 574 }; 575 576 timers17: timers@40014800 { 577 compatible = "st,stm32-timers"; 578 reg = <0x40014800 0x400>; 579 clocks = <&rcc STM32_CLOCK(APB2, 18U)>; 580 resets = <&rctl STM32_RESET(APB2, 18U)>; 581 interrupts = <26 0>; 582 interrupt-names = "global"; 583 st,prescaler = <0>; 584 status = "disabled"; 585 586 pwm { 587 compatible = "st,stm32-pwm"; 588 status = "disabled"; 589 #pwm-cells = <3>; 590 }; 591 592 counter { 593 compatible = "st,stm32-counter"; 594 status = "disabled"; 595 }; 596 }; 597 598 rtc: rtc@40002800 { 599 compatible = "st,stm32-rtc"; 600 reg = <0x40002800 0x400>; 601 interrupts = <41 0>; 602 clocks = <&rcc STM32_CLOCK(APB1, 10U)>; 603 prescaler = <32768>; 604 alarms-count = <2>; 605 alrm-exti-line = <17>; 606 status = "disabled"; 607 }; 608 609 rng: rng@50060800 { 610 compatible = "st,stm32-rng"; 611 reg = <0x50060800 0x400>; 612 interrupts = <90 0>; 613 clocks = <&rcc STM32_CLOCK(AHB2, 26U)>; 614 status = "disabled"; 615 }; 616 617 usb: usb@40005c00 { 618 compatible = "st,stm32-usb"; 619 reg = <0x40005c00 0x400>; 620 interrupts = <20 0>, <19 0>; 621 interrupt-names = "usb", "usbhp"; 622 num-bidir-endpoints = <8>; 623 ram-size = <1024>; 624 phys = <&usb_fs_phy>; 625 clocks = <&rcc STM32_CLOCK(APB1, 23U)>, 626 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; 627 status = "disabled"; 628 }; 629 630 dma1: dma@40020000 { 631 compatible = "st,stm32-dma-v2"; 632 #dma-cells = <3>; 633 reg = <0x40020000 0x400>; 634 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; 635 dma-offset = <0>; 636 status = "disabled"; 637 }; 638 639 dma2: dma@40020400 { 640 compatible = "st,stm32-dma-v2"; 641 #dma-cells = <3>; 642 reg = <0x40020400 0x400>; 643 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; 644 status = "disabled"; 645 }; 646 647 dmamux1: dmamux@40020800 { 648 compatible = "st,stm32-dmamux"; 649 #dma-cells = <3>; 650 reg = <0x40020800 0x400>; 651 interrupts = <94 0>; 652 clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; 653 dma-generators = <4>; 654 dma-requests= <111>; 655 status = "disabled"; 656 }; 657 658 ucpd1: ucpd@4000a000 { 659 compatible = "st,stm32-ucpd"; 660 reg = <0x4000a000 0x400>; 661 clocks = <&rcc STM32_CLOCK(APB1, 4U)>; 662 interrupts = <63 0>; 663 status = "disabled"; 664 }; 665 }; 666 667 die_temp: dietemp { 668 compatible = "st,stm32-temp-cal"; 669 ts-cal1-addr = <0x1FFF75A8>; 670 ts-cal2-addr = <0x1FFF75CA>; 671 ts-cal1-temp = <30>; 672 ts-cal2-temp = <130>; 673 ts-cal-vrefanalog = <3000>; 674 io-channels = <&adc1 16>; 675 status = "disabled"; 676 }; 677 678 vref: vref { 679 compatible = "st,stm32-vref"; 680 vrefint-cal-addr = <0x1FFF75AA>; 681 vrefint-cal-mv = <3000>; 682 io-channels = <&adc1 18>; 683 status = "disabled"; 684 }; 685 686 vbat: vbat { 687 compatible = "st,stm32-vbat"; 688 ratio = <3>; 689 io-channels = <&adc1 17>; 690 status = "disabled"; 691 }; 692 693 usb_fs_phy: usbphy { 694 compatible = "usb-nop-xceiv"; 695 #phy-cells = <0>; 696 }; 697 698 smbus1: smbus1 { 699 compatible = "st,stm32-smbus"; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 i2c = <&i2c1>; 703 status = "disabled"; 704 }; 705 706 smbus2: smbus2 { 707 compatible = "st,stm32-smbus"; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 i2c = <&i2c2>; 711 status = "disabled"; 712 }; 713 714 smbus3: smbus3 { 715 compatible = "st,stm32-smbus"; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 i2c = <&i2c3>; 719 status = "disabled"; 720 }; 721}; 722 723&nvic { 724 arm,num-irq-priority-bits = <4>; 725}; 726
