1/*
2 * Copyright (c) 2020 Thomas Stranger
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/g0/stm32g070.dtsi>
8
9/ {
10	soc {
11		compatible = "st,stm32g0b0", "st,stm32g0", "simple-bus";
12
13		pinctrl: pin-controller@50000000 {
14			gpioe: gpio@50001000 {
15				compatible = "st,stm32-gpio";
16				gpio-controller;
17				#gpio-cells = <2>;
18				reg = <0x50001000 0x400>;
19				clocks = <&rcc STM32_CLOCK(IOP, 4U)>;
20			};
21		};
22
23		usart5: serial@40005000 {
24			compatible = "st,stm32-usart", "st,stm32-uart";
25			reg = <0x40005000 0x400>;
26			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
27			resets = <&rctl STM32_RESET(APB1L, 8U)>;
28			interrupts = <29 0>;
29			status = "disabled";
30		};
31
32		usart6: serial@40013c00 {
33			compatible = "st,stm32-usart", "st,stm32-uart";
34			reg = <0x40013c00 0x400>;
35			clocks = <&rcc STM32_CLOCK(APB1, 9U)>;
36			resets = <&rctl STM32_RESET(APB1L, 9U)>;
37			interrupts = <29 0>;
38			status = "disabled";
39		};
40
41		timers4: timers@40000800 {
42			compatible = "st,stm32-timers";
43			reg = <0x40000800 0x400>;
44			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
45			resets = <&rctl STM32_RESET(APB1L, 2U)>;
46			interrupts = <16 0>;
47			interrupt-names = "global";
48			st,prescaler = <0>;
49			status = "disabled";
50
51			pwm {
52				compatible = "st,stm32-pwm";
53				status = "disabled";
54				#pwm-cells = <3>;
55			};
56		};
57
58		i2c3: i2c@40008800 {
59			compatible = "st,stm32-i2c-v2";
60			clock-frequency = <I2C_BITRATE_STANDARD>;
61			#address-cells = <1>;
62			#size-cells = <0>;
63			reg = <0x40008800 0x400>;
64			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
65			interrupts = <24 0>;
66			interrupt-names = "combined";
67			status = "disabled";
68		};
69
70		spi3: spi@40003c00 {
71			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
72			#address-cells = <1>;
73			#size-cells = <0>;
74			reg = <0x40003c00 0x400>;
75			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
76			interrupts = <26 3>;
77			status = "disabled";
78		};
79
80		dma2: dma@40020400 {
81			compatible = "st,stm32-dma-v2";
82			#dma-cells = <3>;
83			reg = <0x40020400 0x400>;
84			interrupts = <11 0 11 0 11 0 11 0 11 0>;
85			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
86			dma-requests = <5>;
87			dma-offset = <7>;
88			status = "disabled";
89		};
90
91		dmamux1: dmamux@40020800 {
92			dma-channels = <12>;
93		};
94
95		usb: usb@40005c00 {
96			compatible = "st,stm32-usb";
97			reg = <0x40005c00 0x400>;
98			interrupts = <8 0>;
99			interrupt-names = "usb";
100			num-bidir-endpoints = <8>;
101			ram-size = <2048>;
102			phys = <&usb_fs_phy>;
103			clocks = <&rcc STM32_CLOCK(APB1, 13U)>,
104				 <&rcc STM32_SRC_HSI48 USB_SEL(0)>;
105			status = "disabled";
106		};
107	};
108
109	usb_fs_phy: usbphy {
110		compatible = "usb-nop-xceiv";
111		#phy-cells = <0>;
112	};
113
114	smbus3: smbus3 {
115		compatible = "st,stm32-smbus";
116		#address-cells = <1>;
117		#size-cells = <0>;
118		i2c = <&i2c3>;
119		status = "disabled";
120	};
121};
122