1/*
2 * Copyright (c) 2019 STMicroelectronics
3 * Copyright (c) 2019 Centaur Analytics, Inc
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <mem.h>
9#include <freq.h>
10#include <arm/armv7-m.dtsi>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/clock/stm32_common_clocks.h>
13#include <zephyr/dt-bindings/clock/stm32_clock.h>
14#include <zephyr/dt-bindings/i2c/i2c.h>
15#include <zephyr/dt-bindings/pwm/pwm.h>
16#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
17#include <zephyr/dt-bindings/dma/stm32_dma.h>
18#include <zephyr/dt-bindings/reset/stm32mp1_reset.h>
19#include <zephyr/dt-bindings/display/panel.h>
20
21/ {
22	cpus {
23		#address-cells = <1>;
24		#size-cells = <0>;
25
26		cpu0: cpu@0 {
27			device_type = "cpu";
28			compatible = "arm,cortex-m4";
29			reg = <0>;
30		};
31	};
32
33	retram: memory0@0 {
34		compatible = "mmio-sram";
35		reg = <0x00000000 DT_SIZE_K(64)>;
36	};
37	mcusram: memory1@10000000 {
38		compatible = "mmio-sram";
39		reg = <0x10000000 DT_SIZE_K(320)>;
40	};
41
42	soc {
43		compatible = "st,stm32mp157", "st,stm32mp1", "simple-bus";
44
45		rcc: rcc@50000000 {
46			compatible = "st,stm32mp1-rcc";
47			reg = <0x50000000 0x1000>;
48			#clock-cells = <2>;
49
50			rctl: reset-controller {
51				compatible = "st,stm32-rcc-rctl";
52				#reset-cells = <1>;
53				set-bit-to-deassert;
54			};
55		};
56
57		exti: interrupt-controller@5000d000 {
58			compatible = "st,stm32g0-exti", "st,stm32-exti";
59			interrupt-controller;
60			#interrupt-cells = <1>;
61			#address-cells = <1>;
62			reg = <0x5000d000 0x400>;
63			num-lines = <16>;
64			interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
65				     <10 0>, <23 0>, <64 0>, <65 0>,
66				     <66 0>, <67 0>, <40 0>, <42 0>,
67				     <76 0>, <77 0>, <121 0>, <127 0>;
68			interrupt-names = "line0", "line1", "line2", "line3",
69					  "line4", "line5", "line6", "line7",
70					  "line8", "line9", "line10", "line11",
71					  "line12", "line13", "line14", "line15";
72			line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
73				      <4 1>, <5 1>, <6 1>, <7 1>,
74				      <8 1>, <9 1>, <10 1>, <11 1>,
75				      <12 1>, <13 1>, <14 1>, <15 1>;
76		};
77
78		pinctrl: pin-controller@50002000 {
79			compatible = "st,stm32-pinctrl";
80			reg = <0x50002000 0x9000>;
81			#address-cells = <1>;
82			#size-cells = <1>;
83
84			gpioa: gpio@50002000 {
85				compatible = "st,stm32-gpio";
86				reg = <0x50002000 0x400>;
87				gpio-controller;
88				#gpio-cells = <2>;
89				clocks = <&rcc STM32_CLOCK(AHB4, 0U)>;
90			};
91
92			gpiob: gpio@50003000 {
93				compatible = "st,stm32-gpio";
94				reg = <0x50003000 0x400>;
95				gpio-controller;
96				#gpio-cells = <2>;
97				clocks = <&rcc STM32_CLOCK(AHB4, 1U)>;
98			};
99
100			gpioc: gpio@50004000 {
101				compatible = "st,stm32-gpio";
102				reg = <0x50004000 0x400>;
103				gpio-controller;
104				#gpio-cells = <2>;
105				clocks = <&rcc STM32_CLOCK(AHB4, 2U)>;
106			};
107
108			gpiod: gpio@50005000 {
109				compatible = "st,stm32-gpio";
110				reg = <0x50005000 0x400>;
111				gpio-controller;
112				#gpio-cells = <2>;
113				clocks = <&rcc STM32_CLOCK(AHB4, 3U)>;
114			};
115
116			gpioe: gpio@50006000 {
117				compatible = "st,stm32-gpio";
118				reg = <0x50006000 0x400>;
119				gpio-controller;
120				#gpio-cells = <2>;
121				clocks = <&rcc STM32_CLOCK(AHB4, 4U)>;
122			};
123
124			gpiof: gpio@50007000 {
125				compatible = "st,stm32-gpio";
126				reg = <0x50007000 0x400>;
127				gpio-controller;
128				#gpio-cells = <2>;
129				clocks = <&rcc STM32_CLOCK(AHB4, 5U)>;
130			};
131
132			gpiog: gpio@50008000 {
133				compatible = "st,stm32-gpio";
134				reg = <0x50008000 0x400>;
135				gpio-controller;
136				#gpio-cells = <2>;
137				clocks = <&rcc STM32_CLOCK(AHB4, 6U)>;
138			};
139
140			gpioh: gpio@50009000 {
141				compatible = "st,stm32-gpio";
142				reg = <0x50009000 0x400>;
143				gpio-controller;
144				#gpio-cells = <2>;
145				clocks = <&rcc STM32_CLOCK(AHB4, 7U)>;
146			};
147
148			gpioi: gpio@5000a000 {
149				compatible = "st,stm32-gpio";
150				reg = <0x5000a000 0x400>;
151				gpio-controller;
152				#gpio-cells = <2>;
153				clocks = <&rcc STM32_CLOCK(AHB4, 8U)>;
154			};
155
156			gpioj: gpio@5000b000 {
157				compatible = "st,stm32-gpio";
158				reg = <0x5000b000 0x400>;
159				gpio-controller;
160				#gpio-cells = <2>;
161				clocks = <&rcc STM32_CLOCK(AHB4, 9U)>;
162			};
163
164			gpiok: gpio@5000c000 {
165				compatible = "st,stm32-gpio";
166				reg = <0x5000c000 0x400>;
167				gpio-controller;
168				#gpio-cells = <2>;
169				clocks = <&rcc STM32_CLOCK(AHB4, 10U)>;
170			};
171		};
172
173		wwdg: wwdg1: watchdog@4000a000 {
174			compatible = "st,stm32-window-watchdog";
175			reg = <0x4000a000 0x400>;
176			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
177			interrupts = <0 7>;
178			status = "disabled";
179		};
180
181		dma1: dma@48000000 {
182			compatible = "st,stm32-dma-v1";
183			#dma-cells = <4>;
184			reg = <0x48000000 0x400>;
185			clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
186			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
187			dma-offset = <0>;
188			dma-requests = <8>;
189			status = "disabled";
190		};
191
192		dma2: dma@48001000 {
193			compatible = "st,stm32-dma-v1";
194			#dma-cells = <4>;
195			reg = <0x48001000 0x400>;
196			clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
197			interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
198			dma-offset = <8>;
199			dma-requests = <8>;
200			status = "disabled";
201		};
202
203		dmamux: dmamux@48002000 {
204			compatible = "st,stm32-dmamux";
205			#dma-cells = <3>;
206			reg = <0x48002000 0x400>;
207			clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
208			interrupts = <102 0>;
209			dma-channels = <16>;
210			dma-generators = <8>;
211			dma-requests= <108>;
212			status = "disabled";
213		};
214
215		spi1: spi@44004000 {
216			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
217			reg = <0x44004000 0x400>;
218			#address-cells = <1>;
219			#size-cells = <0>;
220			clocks = <&rcc STM32_CLOCK(APB2, 8U)>;
221			interrupts = <35 5>;
222			status = "disabled";
223		};
224
225		spi2: spi@4000b000 {
226			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
227			reg = <0x4000b000 0x400>;
228			#address-cells = <1>;
229			#size-cells = <0>;
230			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
231			interrupts = <36 5>;
232			status = "disabled";
233		};
234
235		spi3: spi@4000c000 {
236			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
237			reg = <0x4000c000 0x400>;
238			#address-cells = <1>;
239			#size-cells = <0>;
240			clocks = <&rcc STM32_CLOCK(APB1, 12U)>;
241			interrupts = <51 5>;
242			status = "disabled";
243		};
244
245		spi4: spi@44005000 {
246			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
247			reg = <0x44005000 0x400>;
248			#address-cells = <1>;
249			#size-cells = <0>;
250			clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
251			interrupts = <84 5>;
252			status = "disabled";
253		};
254
255		spi5: spi@44009000 {
256			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
257			reg = <0x44009000 0x400>;
258			#address-cells = <1>;
259			#size-cells = <0>;
260			clocks = <&rcc STM32_CLOCK(APB2, 10U)>;
261			interrupts = <85 5>;
262			status = "disabled";
263		};
264
265		usart2: serial@4000e000 {
266			compatible = "st,stm32-usart", "st,stm32-uart";
267			reg = <0x4000e000 0x400>;
268			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
269			resets = <&rctl STM32_RESET(APB1, 14U)>;
270			interrupts = <38 0>;
271			status = "disabled";
272		};
273
274		usart3: serial@4000f000 {
275			compatible = "st,stm32-usart", "st,stm32-uart";
276			reg = <0x4000f000 0x400>;
277			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
278			resets = <&rctl STM32_RESET(APB1, 15U)>;
279			interrupts = <39 0>;
280			status = "disabled";
281		};
282
283		uart4: serial@40010000 {
284			compatible = "st,stm32-uart";
285			reg = <0x40010000 0x400>;
286			clocks = <&rcc STM32_CLOCK(APB1, 16U)>;
287			resets = <&rctl STM32_RESET(APB1, 16U)>;
288			interrupts = <52 0>;
289			status = "disabled";
290		};
291
292		uart5: serial@40011000 {
293			compatible = "st,stm32-uart";
294			reg = <0x40011000 0x400>;
295			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
296			resets = <&rctl STM32_RESET(APB1, 17U)>;
297			interrupts = <53 0>;
298			status = "disabled";
299		};
300
301		usart6: serial@44003000 {
302			compatible = "st,stm32-usart", "st,stm32-uart";
303			reg = <0x44003000 0x400>;
304			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
305			resets = <&rctl STM32_RESET(APB2, 13U)>;
306			interrupts = <71 0>;
307			status = "disabled";
308		};
309
310		uart7: serial@40018000 {
311			compatible = "st,stm32-uart";
312			reg = <0x40018000 0x400>;
313			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
314			resets = <&rctl STM32_RESET(APB1, 18U)>;
315			interrupts = <82 0>;
316			status = "disabled";
317		};
318
319		uart8: serial@40019000 {
320			compatible = "st,stm32-uart";
321			reg = <0x40019000 0x400>;
322			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
323			resets = <&rctl STM32_RESET(APB1, 19U)>;
324			interrupts = <83 0>;
325			status = "disabled";
326		};
327
328		i2c5: i2c@40015000 {
329			compatible = "st,stm32-i2c-v2";
330			clock-frequency = <I2C_BITRATE_STANDARD>;
331			reg = <0x40015000 0x400>;
332			#address-cells = <1>;
333			#size-cells = <0>;
334			clocks = <&rcc STM32_CLOCK(APB1, 24U)>;
335			interrupt-names = "event", "error";
336			interrupts = <107 0>, <108 0>;
337			status = "disabled";
338		};
339
340		timers3: timers@40001000 {
341			compatible = "st,stm32-timers";
342			reg = <0x40001000 0x400>;
343			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
344			resets = <&rctl STM32_RESET(APB1, 1U)>;
345			interrupts = <29 0>;
346			interrupt-names = "global";
347			st,prescaler = <0>;
348			status = "disabled";
349
350			pwm {
351				compatible = "st,stm32-pwm";
352				status = "disabled";
353				#pwm-cells = <3>;
354			};
355
356			counter {
357				compatible = "st,stm32-counter";
358				status = "disabled";
359			};
360		};
361
362		timers5: timers@40003000 {
363			compatible = "st,stm32-timers";
364			reg = <0x40003000 0x400>;
365			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
366			resets = <&rctl STM32_RESET(APB1, 3U)>;
367			interrupts = <50 0>;
368			interrupt-names = "global";
369			st,prescaler = <0>;
370			status = "disabled";
371
372			pwm {
373				compatible = "st,stm32-pwm";
374				status = "disabled";
375				#pwm-cells = <3>;
376			};
377
378			counter {
379				compatible = "st,stm32-counter";
380				status = "disabled";
381			};
382		};
383
384		mailbox: mailbox@4c001000 {
385			compatible = "st,stm32-ipcc-mailbox";
386			reg = <0x4c001000 0x400>;
387			clocks = <&rcc STM32_CLOCK(AHB3, 12U)>;
388			interrupts = <103 0>, <104 0>;
389			interrupt-names = "rxo", "txf";
390			status = "disabled";
391		};
392
393		ltdc: display-controller@5a001000 {
394			compatible = "st,stm32-ltdc";
395			reg = <0x5a001000 0x200>;
396			interrupts = <88 0>, <89 0>;
397			interrupt-names = "ltdc", "ltdc_er";
398			clocks = <&rcc STM32_CLOCK(APB4, 0U)>;
399			resets = <&rctl STM32_RESET(APB4, 26U)>;
400			status = "disabled";
401		};
402	};
403
404	smbus5: smbus5 {
405		compatible = "st,stm32-smbus";
406		#address-cells = <1>;
407		#size-cells = <0>;
408		i2c = <&i2c5>;
409		status = "disabled";
410	};
411};
412
413&nvic {
414	arm,num-irq-priority-bits = <4>;
415};
416