Lines Matching +full:stm32 +full:- +full:dma +full:- +full:v2
6 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/clock/stm32l4_clock.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/adc/adc.h>
16 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
17 #include <zephyr/dt-bindings/dma/stm32_dma.h>
18 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
19 #include <zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h>
20 #include <zephyr/dt-bindings/power/stm32_pwr.h>
26 zephyr,flash-controller = &flash;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 compatible = "arm,cortex-m4f";
37 cpu-power-states = <&stop0 &stop1 &stop2>;
40 power-states {
42 compatible = "zephyr,power-state";
43 power-state-name = "suspend-to-idle";
44 substate-id = <1>;
45 min-residency-us = <500>;
48 compatible = "zephyr,power-state";
49 power-state-name = "suspend-to-idle";
50 substate-id = <2>;
51 min-residency-us = <700>;
54 compatible = "zephyr,power-state";
55 power-state-name = "suspend-to-idle";
56 substate-id = <3>;
57 min-residency-us = <1000>;
63 compatible = "mmio-sram";
67 clk_hse: clk-hse {
68 #clock-cells = <0>;
69 compatible = "st,stm32-hse-clock";
73 clk_hsi: clk-hsi {
74 #clock-cells = <0>;
75 compatible = "fixed-clock";
76 clock-frequency = <DT_FREQ_M(16)>;
80 clk_msi: clk-msi {
81 #clock-cells = <0>;
82 compatible = "st,stm32-msi-clock";
83 msi-range = <6>; /* 4MHz (reset value) */
87 clk_lse: clk-lse {
88 #clock-cells = <0>;
89 compatible = "st,stm32-lse-clock";
90 clock-frequency = <32768>;
91 driving-capability = <0>;
95 clk_lsi: clk-lsi {
96 #clock-cells = <0>;
97 compatible = "fixed-clock";
98 clock-frequency = <DT_FREQ_K(32)>;
103 #clock-cells = <0>;
104 compatible = "st,stm32l4-pll-clock";
111 compatible = "st,stm32-clock-mco";
117 flash: flash-controller@40022000 {
118 compatible = "st,stm32-flash-controller", "st,stm32l4-flash-controller";
123 #address-cells = <1>;
124 #size-cells = <1>;
127 compatible = "st,stm32-nv-flash", "soc-nv-flash";
129 write-block-size = <8>;
130 erase-block-size = <2048>;
132 max-erase-time = <25>;
137 compatible = "st,stm32-rcc";
138 #clock-cells = <2>;
141 rctl: reset-controller {
142 compatible = "st,stm32-rcc-rctl";
143 #reset-cells = <1>;
147 exti: interrupt-controller@40010400 {
148 compatible = "st,stm32-exti";
149 interrupt-controller;
150 #interrupt-cells = <1>;
151 #address-cells = <1>;
153 num-lines = <16>;
156 interrupt-names = "line0", "line1", "line2", "line3",
157 "line4", "line5-9", "line10-15";
158 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
162 pinctrl: pin-controller@48000000 {
163 compatible = "st,stm32-pinctrl";
164 #address-cells = <1>;
165 #size-cells = <1>;
169 compatible = "st,stm32-gpio";
170 gpio-controller;
171 #gpio-cells = <2>;
177 compatible = "st,stm32-gpio";
178 gpio-controller;
179 #gpio-cells = <2>;
185 compatible = "st,stm32-gpio";
186 gpio-controller;
187 #gpio-cells = <2>;
193 compatible = "st,stm32-gpio";
194 gpio-controller;
195 #gpio-cells = <2>;
202 compatible = "st,stm32-watchdog";
208 compatible = "st,stm32-window-watchdog";
216 compatible = "st,stm32-usart", "st,stm32-uart";
225 compatible = "st,stm32-usart", "st,stm32-uart";
234 compatible = "st,stm32-lpuart", "st,stm32-uart";
243 compatible = "st,stm32-i2c-v2";
244 clock-frequency = <I2C_BITRATE_STANDARD>;
245 #address-cells = <1>;
246 #size-cells = <0>;
250 interrupt-names = "event", "error";
255 compatible = "st,stm32-i2c-v2";
256 clock-frequency = <I2C_BITRATE_STANDARD>;
257 #address-cells = <1>;
258 #size-cells = <0>;
262 interrupt-names = "event", "error";
267 compatible = "st,stm32-qspi";
268 #address-cells = <1>;
269 #size-cells = <0>;
277 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
278 #address-cells = <1>;
279 #size-cells = <0>;
288 compatible = "st,stm32-timers";
293 interrupt-names = "brk", "up", "trgcom", "cc";
298 compatible = "st,stm32-pwm";
300 #pwm-cells = <3>;
305 compatible = "st,stm32-timers";
310 interrupt-names = "global";
315 compatible = "st,stm32-pwm";
317 #pwm-cells = <3>;
321 compatible = "st,stm32-counter";
327 compatible = "st,stm32-timers";
332 interrupt-names = "global";
337 compatible = "st,stm32-counter";
343 compatible = "st,stm32-timers";
348 interrupt-names = "global";
353 compatible = "st,stm32-pwm";
355 #pwm-cells = <3>;
359 compatible = "st,stm32-counter";
365 compatible = "st,stm32-timers";
370 interrupt-names = "global";
375 compatible = "st,stm32-pwm";
377 #pwm-cells = <3>;
381 compatible = "st,stm32-counter";
387 compatible = "st,stm32-rtc";
392 alarms-count = <2>;
393 alrm-exti-line = <18>;
398 compatible = "st,stm32-adc";
403 #io-channel-cells = <1>;
408 sampling-times = <3 7 13 25 48 93 248 641>;
409 st,adc-sequencer = "FULLY_CONFIGURABLE";
410 st,adc-oversampler = "OVERSAMPLER_MINIMAL";
414 compatible = "st,stm32-adc";
419 #io-channel-cells = <1>;
424 sampling-times = <3 7 13 25 48 93 248 641>;
425 st,adc-sequencer = "FULLY_CONFIGURABLE";
426 st,adc-oversampler = "OVERSAMPLER_MINIMAL";
429 dma1: dma@40020000 {
430 compatible = "st,stm32-dma-v2";
431 #dma-cells = <3>;
435 dma-requests = <7>;
439 dma2: dma@40020400 {
440 compatible = "st,stm32-dma-v2";
441 #dma-cells = <3>;
445 dma-requests = <7>;
450 compatible = "st,stm32-lptim";
452 #address-cells = <1>;
453 #size-cells = <0>;
456 interrupt-names = "wakeup";
461 compatible = "st,stm32-lptim";
462 #address-cells = <1>;
463 #size-cells = <0>;
467 interrupt-names = "wakeup";
472 compatible = "st,stm32-rng";
477 * clock to be enabled with msi-range = <11>;
484 compatible = "st,stm32-pwr";
488 wkup-pins-nb = <5>; /* 5 system wake-up pins */
489 wkup-pins-pol;
490 wkup-pins-pupd;
492 #address-cells = <1>;
493 #size-cells = <0>;
495 wkup-pin@1 {
499 wkup-pin@2 {
503 wkup-pin@3 {
507 wkup-pin@4 {
511 wkup-pin@5 {
518 compatible = "st,stm32-temp-cal";
519 ts-cal1-addr = <0x1FFF75A8>;
520 ts-cal2-addr = <0x1FFF75CA>;
521 ts-cal1-temp = <30>;
522 ts-cal2-temp = <130>;
523 ts-cal-vrefanalog = <3000>;
524 io-channels = <&adc1 17>;
529 compatible = "st,stm32-vref";
530 vrefint-cal-addr = <0x1FFF75AA>;
531 vrefint-cal-mv = <3000>;
532 io-channels = <&adc1 0>;
537 compatible = "st,stm32-vbat";
539 io-channels = <&adc1 18>;
544 compatible = "st,stm32-smbus";
545 #address-cells = <1>;
546 #size-cells = <0>;
552 compatible = "st,stm32-smbus";
553 #address-cells = <1>;
554 #size-cells = <0>;
561 arm,num-irq-priority-bits = <4>;