1/* 2 * Copyright (c) 2017 Linaro Limited 3 * Copyright (c) 2019 Centaur Analytics, Inc 4 * Copyright (c) 2024 STMicroelectronics 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 10#include <arm/armv7-m.dtsi> 11#include <zephyr/dt-bindings/clock/stm32l4_clock.h> 12#include <zephyr/dt-bindings/i2c/i2c.h> 13#include <zephyr/dt-bindings/gpio/gpio.h> 14#include <zephyr/dt-bindings/pwm/pwm.h> 15#include <zephyr/dt-bindings/adc/adc.h> 16#include <zephyr/dt-bindings/pwm/stm32_pwm.h> 17#include <zephyr/dt-bindings/dma/stm32_dma.h> 18#include <zephyr/dt-bindings/adc/stm32l4_adc.h> 19#include <zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h> 20#include <zephyr/dt-bindings/power/stm32_pwr.h> 21#include <freq.h> 22 23/ { 24 chosen { 25 zephyr,entropy = &rng; 26 zephyr,flash-controller = &flash; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-m4f"; 36 reg = <0>; 37 cpu-power-states = <&stop0 &stop1 &stop2>; 38 }; 39 40 power-states { 41 stop0: state0 { 42 compatible = "zephyr,power-state"; 43 power-state-name = "suspend-to-idle"; 44 substate-id = <1>; 45 min-residency-us = <500>; 46 }; 47 stop1: state1 { 48 compatible = "zephyr,power-state"; 49 power-state-name = "suspend-to-idle"; 50 substate-id = <2>; 51 min-residency-us = <700>; 52 }; 53 stop2: state2 { 54 compatible = "zephyr,power-state"; 55 power-state-name = "suspend-to-idle"; 56 substate-id = <3>; 57 min-residency-us = <1000>; 58 }; 59 }; 60 }; 61 62 sram0: memory@20000000 { 63 compatible = "mmio-sram"; 64 }; 65 66 clocks { 67 clk_hse: clk-hse { 68 #clock-cells = <0>; 69 compatible = "st,stm32-hse-clock"; 70 status = "disabled"; 71 }; 72 73 clk_hsi: clk-hsi { 74 #clock-cells = <0>; 75 compatible = "fixed-clock"; 76 clock-frequency = <DT_FREQ_M(16)>; 77 status = "disabled"; 78 }; 79 80 clk_msi: clk-msi { 81 #clock-cells = <0>; 82 compatible = "st,stm32-msi-clock"; 83 msi-range = <6>; /* 4MHz (reset value) */ 84 status = "disabled"; 85 }; 86 87 clk_lse: clk-lse { 88 #clock-cells = <0>; 89 compatible = "st,stm32-lse-clock"; 90 clock-frequency = <32768>; 91 driving-capability = <0>; 92 status = "disabled"; 93 }; 94 95 clk_lsi: clk-lsi { 96 #clock-cells = <0>; 97 compatible = "fixed-clock"; 98 clock-frequency = <DT_FREQ_K(32)>; 99 status = "disabled"; 100 }; 101 102 pll: pll { 103 #clock-cells = <0>; 104 compatible = "st,stm32l4-pll-clock"; 105 status = "disabled"; 106 }; 107 }; 108 109 mcos { 110 mco1: mco1 { 111 compatible = "st,stm32-clock-mco"; 112 status = "disabled"; 113 }; 114 }; 115 116 soc { 117 flash: flash-controller@40022000 { 118 compatible = "st,stm32-flash-controller", "st,stm32l4-flash-controller"; 119 reg = <0x40022000 0x400>; 120 interrupts = <4 0>; 121 clocks = <&rcc STM32_CLOCK(AHB1, 8U)>; 122 123 #address-cells = <1>; 124 #size-cells = <1>; 125 126 flash0: flash@8000000 { 127 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 128 129 write-block-size = <8>; 130 erase-block-size = <2048>; 131 /* maximum erase time(ms) for a 2K sector */ 132 max-erase-time = <25>; 133 }; 134 }; 135 136 rcc: rcc@40021000 { 137 compatible = "st,stm32-rcc"; 138 #clock-cells = <2>; 139 reg = <0x40021000 0x400>; 140 141 rctl: reset-controller { 142 compatible = "st,stm32-rcc-rctl"; 143 #reset-cells = <1>; 144 }; 145 }; 146 147 exti: interrupt-controller@40010400 { 148 compatible = "st,stm32-exti"; 149 interrupt-controller; 150 #interrupt-cells = <1>; 151 #address-cells = <1>; 152 reg = <0x40010400 0x400>; 153 num-lines = <16>; 154 interrupts = <6 0>, <7 0>, <8 0>, <9 0>, 155 <10 0>, <23 0>, <40 0>; 156 interrupt-names = "line0", "line1", "line2", "line3", 157 "line4", "line5-9", "line10-15"; 158 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 159 <4 1>, <5 5>, <10 6>; 160 }; 161 162 pinctrl: pin-controller@48000000 { 163 compatible = "st,stm32-pinctrl"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 reg = <0x48000000 0x2000>; 167 168 gpioa: gpio@48000000 { 169 compatible = "st,stm32-gpio"; 170 gpio-controller; 171 #gpio-cells = <2>; 172 reg = <0x48000000 0x400>; 173 clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; 174 }; 175 176 gpiob: gpio@48000400 { 177 compatible = "st,stm32-gpio"; 178 gpio-controller; 179 #gpio-cells = <2>; 180 reg = <0x48000400 0x400>; 181 clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; 182 }; 183 184 gpioc: gpio@48000800 { 185 compatible = "st,stm32-gpio"; 186 gpio-controller; 187 #gpio-cells = <2>; 188 reg = <0x48000800 0x400>; 189 clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; 190 }; 191 192 gpioh: gpio@48001c00 { 193 compatible = "st,stm32-gpio"; 194 gpio-controller; 195 #gpio-cells = <2>; 196 reg = <0x48001c00 0x400>; 197 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; 198 }; 199 }; 200 201 iwdg: watchdog@40003000 { 202 compatible = "st,stm32-watchdog"; 203 reg = <0x40003000 0x400>; 204 status = "disabled"; 205 }; 206 207 wwdg: watchdog@40002c00 { 208 compatible = "st,stm32-window-watchdog"; 209 reg = <0x40002C00 0x400>; 210 clocks = <&rcc STM32_CLOCK(APB1, 11U)>; 211 interrupts = <0 7>; 212 status = "disabled"; 213 }; 214 215 usart1: serial@40013800 { 216 compatible = "st,stm32-usart", "st,stm32-uart"; 217 reg = <0x40013800 0x400>; 218 clocks = <&rcc STM32_CLOCK(APB2, 14U)>; 219 resets = <&rctl STM32_RESET(APB2, 14U)>; 220 interrupts = <37 0>; 221 status = "disabled"; 222 }; 223 224 usart2: serial@40004400 { 225 compatible = "st,stm32-usart", "st,stm32-uart"; 226 reg = <0x40004400 0x400>; 227 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 228 resets = <&rctl STM32_RESET(APB1L, 17U)>; 229 interrupts = <38 0>; 230 status = "disabled"; 231 }; 232 233 lpuart1: serial@40008000 { 234 compatible = "st,stm32-lpuart", "st,stm32-uart"; 235 reg = <0x40008000 0x400>; 236 clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>; 237 resets = <&rctl STM32_RESET(APB1H, 0U)>; 238 interrupts = <70 0>; 239 status = "disabled"; 240 }; 241 242 i2c1: i2c@40005400 { 243 compatible = "st,stm32-i2c-v2"; 244 clock-frequency = <I2C_BITRATE_STANDARD>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 reg = <0x40005400 0x400>; 248 clocks = <&rcc STM32_CLOCK(APB1, 21U)>; 249 interrupts = <31 0>, <32 0>; 250 interrupt-names = "event", "error"; 251 status = "disabled"; 252 }; 253 254 i2c3: i2c@40005c00 { 255 compatible = "st,stm32-i2c-v2"; 256 clock-frequency = <I2C_BITRATE_STANDARD>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 reg = <0x40005c00 0x400>; 260 clocks = <&rcc STM32_CLOCK(APB1, 23U)>; 261 interrupts = <72 0>, <73 0>; 262 interrupt-names = "event", "error"; 263 status = "disabled"; 264 }; 265 266 quadspi: quadspi@a0001000 { 267 compatible = "st,stm32-qspi"; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 reg = <0xa0001000 0x400>; 271 interrupts = <71 0>; 272 clocks = <&rcc STM32_CLOCK(AHB3, 8U)>; 273 status = "disabled"; 274 }; 275 276 spi1: spi@40013000 { 277 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 reg = <0x40013000 0x400>; 281 interrupts = <35 5>; 282 clocks = <&rcc STM32_CLOCK(APB2, 12U)>; 283 status = "disabled"; 284 }; 285 286 287 timers1: timers@40012c00 { 288 compatible = "st,stm32-timers"; 289 reg = <0x40012c00 0x400>; 290 clocks = <&rcc STM32_CLOCK(APB2, 11U)>; 291 resets = <&rctl STM32_RESET(APB2, 11U)>; 292 interrupts = <24 0>, <25 0>, <26 0>, <27 0>; 293 interrupt-names = "brk", "up", "trgcom", "cc"; 294 st,prescaler = <0>; 295 status = "disabled"; 296 297 pwm { 298 compatible = "st,stm32-pwm"; 299 status = "disabled"; 300 #pwm-cells = <3>; 301 }; 302 }; 303 304 timers2: timers@40000000 { 305 compatible = "st,stm32-timers"; 306 reg = <0x40000000 0x400>; 307 clocks = <&rcc STM32_CLOCK(APB1, 0U)>; 308 resets = <&rctl STM32_RESET(APB1L, 0U)>; 309 interrupts = <28 0>; 310 interrupt-names = "global"; 311 st,prescaler = <0>; 312 status = "disabled"; 313 314 pwm { 315 compatible = "st,stm32-pwm"; 316 status = "disabled"; 317 #pwm-cells = <3>; 318 }; 319 320 counter { 321 compatible = "st,stm32-counter"; 322 status = "disabled"; 323 }; 324 }; 325 326 timers6: timers@40001000 { 327 compatible = "st,stm32-timers"; 328 reg = <0x40001000 0x400>; 329 clocks = <&rcc STM32_CLOCK(APB1, 4U)>; 330 resets = <&rctl STM32_RESET(APB1L, 4U)>; 331 interrupts = <54 0>; 332 interrupt-names = "global"; 333 st,prescaler = <0>; 334 status = "disabled"; 335 336 counter { 337 compatible = "st,stm32-counter"; 338 status = "disabled"; 339 }; 340 }; 341 342 timers15: timers@40014000 { 343 compatible = "st,stm32-timers"; 344 reg = <0x40014000 0x400>; 345 clocks = <&rcc STM32_CLOCK(APB2, 16U)>; 346 resets = <&rctl STM32_RESET(APB2, 16U)>; 347 interrupts = <24 0>; 348 interrupt-names = "global"; 349 st,prescaler = <0>; 350 status = "disabled"; 351 352 pwm { 353 compatible = "st,stm32-pwm"; 354 status = "disabled"; 355 #pwm-cells = <3>; 356 }; 357 358 counter { 359 compatible = "st,stm32-counter"; 360 status = "disabled"; 361 }; 362 }; 363 364 timers16: timers@40014400 { 365 compatible = "st,stm32-timers"; 366 reg = <0x40014400 0x400>; 367 clocks = <&rcc STM32_CLOCK(APB2, 17U)>; 368 resets = <&rctl STM32_RESET(APB2, 17U)>; 369 interrupts = <25 0>; 370 interrupt-names = "global"; 371 st,prescaler = <0>; 372 status = "disabled"; 373 374 pwm { 375 compatible = "st,stm32-pwm"; 376 status = "disabled"; 377 #pwm-cells = <3>; 378 }; 379 380 counter { 381 compatible = "st,stm32-counter"; 382 status = "disabled"; 383 }; 384 }; 385 386 rtc: rtc@40002800 { 387 compatible = "st,stm32-rtc"; 388 reg = <0x40002800 0x400>; 389 interrupts = <41 0>; 390 clocks = <&rcc STM32_CLOCK(APB1, 28U)>; 391 prescaler = <32768>; 392 alarms-count = <2>; 393 alrm-exti-line = <18>; 394 status = "disabled"; 395 }; 396 397 adc1: adc@50040000 { 398 compatible = "st,stm32-adc"; 399 reg = <0x50040000 0x100>; 400 clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; 401 interrupts = <18 0>; 402 status = "disabled"; 403 #io-channel-cells = <1>; 404 resolutions = <STM32_ADC_RES(12, 0x00) 405 STM32_ADC_RES(10, 0x01) 406 STM32_ADC_RES(8, 0x02) 407 STM32_ADC_RES(6, 0x03)>; 408 sampling-times = <3 7 13 25 48 93 248 641>; 409 st,adc-sequencer = "FULLY_CONFIGURABLE"; 410 st,adc-oversampler = "OVERSAMPLER_MINIMAL"; 411 }; 412 413 adc2: adc@50040100 { 414 compatible = "st,stm32-adc"; 415 reg = <0x50040100 0x100>; 416 clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; 417 interrupts = <18 0>; 418 status = "disabled"; 419 #io-channel-cells = <1>; 420 resolutions = <STM32_ADC_RES(12, 0x00) 421 STM32_ADC_RES(10, 0x01) 422 STM32_ADC_RES(8, 0x02) 423 STM32_ADC_RES(6, 0x03)>; 424 sampling-times = <3 7 13 25 48 93 248 641>; 425 st,adc-sequencer = "FULLY_CONFIGURABLE"; 426 st,adc-oversampler = "OVERSAMPLER_MINIMAL"; 427 }; 428 429 dma1: dma@40020000 { 430 compatible = "st,stm32-dma-v2"; 431 #dma-cells = <3>; 432 reg = <0x40020000 0x400>; 433 interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; 434 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; 435 dma-requests = <7>; 436 status = "disabled"; 437 }; 438 439 dma2: dma@40020400 { 440 compatible = "st,stm32-dma-v2"; 441 #dma-cells = <3>; 442 reg = <0x40020400 0x400>; 443 interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0>; 444 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; 445 dma-requests = <7>; 446 status = "disabled"; 447 }; 448 449 lptim1: timers@40007c00 { 450 compatible = "st,stm32-lptim"; 451 clocks = <&rcc STM32_CLOCK(APB1, 31U)>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 reg = <0x40007c00 0x400>; 455 interrupts = <65 1>; 456 interrupt-names = "wakeup"; 457 status = "disabled"; 458 }; 459 460 lptim2: timers@40009400 { 461 compatible = "st,stm32-lptim"; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 reg = <0x40009400 0x400>; 465 clocks = <&rcc STM32_CLOCK(APB1_2, 5U)>; 466 interrupts = <66 1>; 467 interrupt-names = "wakeup"; 468 status = "disabled"; 469 }; 470 471 rng: rng@50060800 { 472 compatible = "st,stm32-rng"; 473 reg = <0x50060800 0x400>; 474 interrupts = <80 0>; 475 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>, 476 /* Following domain clock setting requires MSI 477 * clock to be enabled with msi-range = <11>; 478 */ 479 <&rcc STM32_SRC_MSI CLK48_SEL(3)>; 480 status = "disabled"; 481 }; 482 483 pwr: power@40007000 { 484 compatible = "st,stm32-pwr"; 485 reg = <0x40007000 0x400>; /* PWR register bank */ 486 status = "disabled"; 487 488 wkup-pins-nb = <5>; /* 5 system wake-up pins */ 489 wkup-pins-pol; 490 wkup-pins-pupd; 491 492 #address-cells = <1>; 493 #size-cells = <0>; 494 495 wkup-pin@1 { 496 reg = <0x1>; 497 }; 498 499 wkup-pin@2 { 500 reg = <0x2>; 501 }; 502 503 wkup-pin@3 { 504 reg = <0x3>; 505 }; 506 507 wkup-pin@4 { 508 reg = <0x4>; 509 }; 510 511 wkup-pin@5 { 512 reg = <0x5>; 513 }; 514 }; 515 }; 516 517 die_temp: dietemp { 518 compatible = "st,stm32-temp-cal"; 519 ts-cal1-addr = <0x1FFF75A8>; 520 ts-cal2-addr = <0x1FFF75CA>; 521 ts-cal1-temp = <30>; 522 ts-cal2-temp = <130>; 523 ts-cal-vrefanalog = <3000>; 524 io-channels = <&adc1 17>; 525 status = "disabled"; 526 }; 527 528 vref: vref { 529 compatible = "st,stm32-vref"; 530 vrefint-cal-addr = <0x1FFF75AA>; 531 vrefint-cal-mv = <3000>; 532 io-channels = <&adc1 0>; 533 status = "disabled"; 534 }; 535 536 vbat: vbat { 537 compatible = "st,stm32-vbat"; 538 ratio = <3>; 539 io-channels = <&adc1 18>; 540 status = "disabled"; 541 }; 542 543 smbus1: smbus1 { 544 compatible = "st,stm32-smbus"; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 i2c = <&i2c1>; 548 status = "disabled"; 549 }; 550 551 smbus3: smbus3 { 552 compatible = "st,stm32-smbus"; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 i2c = <&i2c3>; 556 status = "disabled"; 557 }; 558}; 559 560&nvic { 561 arm,num-irq-priority-bits = <4>; 562}; 563
