1/*
2 * Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com>
3 * Copyright (c) 2019 Centaur Analytics, Inc
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <arm/armv6-m.dtsi>
9#include <zephyr/dt-bindings/clock/stm32l0_clock.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/pwm/pwm.h>
13#include <zephyr/dt-bindings/adc/adc.h>
14#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15#include <zephyr/dt-bindings/dma/stm32_dma.h>
16#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
17#include <zephyr/dt-bindings/reset/stm32l0_reset.h>
18#include <freq.h>
19
20/ {
21	chosen {
22		zephyr,flash-controller = &flash;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu0: cpu@0 {
30			device_type = "cpu";
31			compatible = "arm,cortex-m0+";
32			reg = <0>;
33			cpu-power-states = <&stop>;
34		};
35
36		power-states {
37			stop: stop {
38				compatible = "zephyr,power-state";
39				power-state-name = "suspend-to-idle";
40				min-residency-us = <2000>;
41				exit-latency-us = <750>;
42			};
43		};
44	};
45
46	sram0: memory@20000000 {
47		compatible = "mmio-sram";
48	};
49
50	clocks {
51		clk_hse: clk-hse {
52			#clock-cells = <0>;
53			compatible = "st,stm32-hse-clock";
54			status = "disabled";
55		};
56
57		clk_hsi: clk-hsi {
58			#clock-cells = <0>;
59			compatible = "fixed-clock";
60			clock-frequency = <DT_FREQ_M(16)>;
61			status = "disabled";
62		};
63
64		clk_msi: clk-msi {
65			#clock-cells = <0>;
66			compatible = "st,stm32l0-msi-clock";
67			msi-range = <5>; /* 2.1MHz (reset value) */
68			status = "disabled";
69		};
70
71		clk_lse: clk-lse {
72			#clock-cells = <0>;
73			compatible = "st,stm32-lse-clock";
74			clock-frequency = <32768>;
75			driving-capability = <0>;
76			status = "disabled";
77		};
78
79		clk_lsi: clk-lsi {
80			#clock-cells = <0>;
81			compatible = "fixed-clock";
82			clock-frequency = <DT_FREQ_K(37)>;
83			status = "disabled";
84		};
85
86		pll: pll {
87			#clock-cells = <0>;
88			compatible = "st,stm32l0-pll-clock";
89			status = "disabled";
90		};
91	};
92
93	soc {
94		rtc: rtc@40002800 {
95			compatible = "st,stm32-rtc";
96			reg = <0x40002800 0x400>;
97			interrupts = <2 0>;
98			clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
99			prescaler = <32768>;
100			alarms-count = <2>;
101			alrm-exti-line = <17>;
102			status = "disabled";
103
104			bbram: backup_regs {
105				compatible = "st,stm32-bbram";
106				st,backup-regs = <5>;
107				status = "disabled";
108			};
109		};
110
111		flash: flash-controller@40022000 {
112			compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
113			reg = <0x40022000 0x400>;
114			interrupts = <3 0>;
115
116			#address-cells = <1>;
117			#size-cells = <1>;
118
119			flash0: flash@8000000 {
120				compatible = "st,stm32l0-nv-flash", "st,stm32-nv-flash",
121					     "soc-nv-flash";
122
123				write-block-size = <4>;
124				/* maximum erase time(ms) for a 128B page */
125				max-erase-time = <4>;
126			};
127		};
128
129		rcc: rcc@40021000 {
130			compatible = "st,stm32-rcc";
131			#clock-cells = <2>;
132			reg = <0x40021000 0x400>;
133
134			rctl: reset-controller {
135				compatible = "st,stm32-rcc-rctl";
136				#reset-cells = <1>;
137			};
138		};
139
140		exti: interrupt-controller@40010400 {
141			compatible = "st,stm32-exti";
142			interrupt-controller;
143			#interrupt-cells = <1>;
144			#address-cells = <1>;
145			reg = <0x40010400 0x400>;
146			num-lines = <16>;
147			interrupts = <5 0>, <6 0>, <7 0>;
148			interrupt-names = "line0-1", "line2-3", "line4-15";
149			line-ranges = <0 2>, <2 2>, <4 12>;
150		};
151
152		pinctrl: pin-controller@50000000 {
153			compatible = "st,stm32-pinctrl";
154			#address-cells = <1>;
155			#size-cells = <1>;
156			reg = <0x50000000 0x2000>;
157
158			gpioa: gpio@50000000 {
159				compatible = "st,stm32-gpio";
160				gpio-controller;
161				#gpio-cells = <2>;
162				reg = <0x50000000 0x400>;
163				clocks = <&rcc STM32_CLOCK(IOP, 0U)>;
164			};
165
166			gpiob: gpio@50000400 {
167				compatible = "st,stm32-gpio";
168				gpio-controller;
169				#gpio-cells = <2>;
170				reg = <0x50000400 0x400>;
171				clocks = <&rcc STM32_CLOCK(IOP, 1U)>;
172			};
173
174			gpioc: gpio@50000800 {
175				compatible = "st,stm32-gpio";
176				gpio-controller;
177				#gpio-cells = <2>;
178				reg = <0x50000800 0x400>;
179				clocks = <&rcc STM32_CLOCK(IOP, 2U)>;
180			};
181
182			gpiod: gpio@50000c00 {
183				compatible = "st,stm32-gpio";
184				gpio-controller;
185				#gpio-cells = <2>;
186				reg = <0x50000c00 0x400>;
187				clocks = <&rcc STM32_CLOCK(IOP, 3U)>;
188			};
189
190			gpioh: gpio@50001c00 {
191				compatible = "st,stm32-gpio";
192				gpio-controller;
193				#gpio-cells = <2>;
194				reg = <0x50001c00 0x400>;
195				clocks = <&rcc STM32_CLOCK(IOP, 7U)>;
196			};
197		};
198
199		iwdg: watchdog@40003000 {
200			compatible = "st,stm32-watchdog";
201			reg = <0x40003000 0x400>;
202			status = "disabled";
203		};
204
205		wwdg: watchdog@40002c00 {
206			compatible = "st,stm32-window-watchdog";
207			reg = <0x40002C00 0x400>;
208			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
209			interrupts = <0 2>;
210			status = "disabled";
211		};
212
213		usart2: serial@40004400 {
214			compatible = "st,stm32-usart", "st,stm32-uart";
215			reg = <0x40004400 0x400>;
216			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
217			resets = <&rctl STM32_RESET(APB1, 17U)>;
218			interrupts = <28 0>;
219			status = "disabled";
220		};
221
222		lpuart1: serial@40004800 {
223			compatible = "st,stm32-lpuart", "st,stm32-uart";
224			reg = <0x40004800 0x400>;
225			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
226			resets = <&rctl STM32_RESET(APB1, 18U)>;
227			interrupts = <29 0>;
228			status = "disabled";
229		};
230
231		i2c1: i2c@40005400 {
232			compatible = "st,stm32-i2c-v2";
233			clock-frequency = <I2C_BITRATE_STANDARD>;
234			#address-cells = <1>;
235			#size-cells = <0>;
236			reg = <0x40005400 0x400>;
237			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
238			interrupts = <23 0>;
239			interrupt-names = "combined";
240			status = "disabled";
241		};
242
243		spi1: spi@40013000 {
244			compatible = "st,stm32-spi";
245			#address-cells = <1>;
246			#size-cells = <0>;
247			reg = <0x40013000 0x400>;
248			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
249			interrupts = <25 3>;
250			status = "disabled";
251		};
252
253		timers2: timers@40000000 {
254			compatible = "st,stm32-timers";
255			reg = <0x40000000 0x400>;
256			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
257			resets = <&rctl STM32_RESET(APB1, 0U)>;
258			interrupts = <15 0>;
259			interrupt-names = "global";
260			st,prescaler = <0>;
261			status = "disabled";
262
263			pwm {
264				compatible = "st,stm32-pwm";
265				status = "disabled";
266				#pwm-cells = <3>;
267			};
268
269			counter {
270				compatible = "st,stm32-counter";
271				status = "disabled";
272			};
273		};
274
275		timers21: timers@40010800 {
276			compatible = "st,stm32-timers";
277			reg = <0x40010800 0x400>;
278			clocks = <&rcc STM32_CLOCK(APB2, 2U)>;
279			resets = <&rctl STM32_RESET(APB2, 2U)>;
280			interrupts = <20 0>;
281			interrupt-names = "global";
282			st,prescaler = <0>;
283			status = "disabled";
284
285			pwm {
286				compatible = "st,stm32-pwm";
287				status = "disabled";
288				#pwm-cells = <3>;
289			};
290
291			counter {
292				compatible = "st,stm32-counter";
293				status = "disabled";
294			};
295		};
296
297		lptim1: timers@40007c00 {
298			compatible = "st,stm32-lptim";
299			clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
300			#address-cells = <1>;
301			#size-cells = <0>;
302			reg = <0x40007c00 0x400>;
303			interrupts = <13 1>;
304			interrupt-names = "wakeup";
305			status = "disabled";
306		};
307
308		adc1: adc@40012400 {
309			compatible = "st,stm32-adc";
310			reg = <0x40012400 0x400>;
311			clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
312			interrupts = <12 0>;
313			status = "disabled";
314			#io-channel-cells = <1>;
315			resolutions = <STM32_ADC_RES(12, 0x00)
316				       STM32_ADC_RES(10, 0x01)
317				       STM32_ADC_RES(8, 0x02)
318				       STM32_ADC_RES(6, 0x03)>;
319			sampling-times = <2 4 8 13 20 40 80 161>;
320			num-sampling-time-common-channels = <1>;
321			st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
322			st,adc-oversampler = "OVERSAMPLER_MINIMAL";
323		};
324
325		dma1: dma@40020000 {
326			compatible = "st,stm32-dma-v2";
327			#dma-cells = <3>;
328			reg = <0x40020000 0x400>;
329			interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
330			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
331			status = "disabled";
332		};
333
334		eeprom: eeprom@8080000{
335			compatible = "st,stm32-eeprom";
336			status = "disabled";
337		};
338	};
339
340	die_temp: dietemp {
341		compatible = "st,stm32-temp-cal";
342		ts-cal1-addr = <0x1FF8007A>;
343		ts-cal2-addr = <0x1FF8007E>;
344		ts-cal1-temp = <30>;
345		ts-cal2-temp = <130>;
346		ts-cal-vrefanalog = <3000>;
347		io-channels = <&adc1 18>;
348		status = "disabled";
349	};
350
351	vref: vref {
352		compatible = "st,stm32-vref";
353		vrefint-cal-addr = <0x1FF80078>;
354		vrefint-cal-mv = <3000>;
355		io-channels = <&adc1 17>;
356		status = "disabled";
357	};
358
359	smbus1: smbus1 {
360		compatible = "st,stm32-smbus";
361		#address-cells = <1>;
362		#size-cells = <0>;
363		i2c = <&i2c1>;
364		status = "disabled";
365	};
366};
367
368&nvic {
369	arm,num-irq-priority-bits = <2>;
370};
371