1/* 2 * Copyright (c) 2019 Linaro Limited 3 * Copyright (c) 2019 Centaur Analytics, Inc 4 * Copyright (c) 2020 Teslabs Engineering S.L. 5 * Copyright (c) 2024 STMicroelectronics 6 * 7 * SPDX-License-Identifier: Apache-2.0 8 */ 9 10#include <arm/armv7-m.dtsi> 11#include <zephyr/dt-bindings/clock/stm32h7_clock.h> 12#include <zephyr/dt-bindings/gpio/gpio.h> 13#include <zephyr/dt-bindings/i2c/i2c.h> 14#include <zephyr/dt-bindings/pwm/pwm.h> 15#include <zephyr/dt-bindings/pwm/stm32_pwm.h> 16#include <zephyr/dt-bindings/dma/stm32_dma.h> 17#include <zephyr/dt-bindings/adc/stm32h7_adc.h> 18#include <zephyr/dt-bindings/reset/stm32h7_reset.h> 19#include <zephyr/dt-bindings/adc/adc.h> 20#include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h> 21#include <zephyr/dt-bindings/memory-attr/memory-attr.h> 22#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> 23#include <freq.h> 24 25/ { 26 chosen { 27 zephyr,entropy = &rng; 28 zephyr,flash-controller = &flash; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-m7"; 38 reg = <0>; 39 #address-cells = <1>; 40 #size-cells = <1>; 41 42 mpu: mpu@e000ed90 { 43 compatible = "arm,armv7m-mpu"; 44 reg = <0xe000ed90 0x40>; 45 }; 46 }; 47 }; 48 49 ext_memory: memory@90000000 { 50 compatible = "zephyr,memory-region"; 51 reg = <0x90000000 DT_SIZE_M(256)>; /* max addressable area */ 52 zephyr,memory-region = "EXTMEM"; 53 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>; 54 }; 55 56 clocks { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 clk_hse: clk-hse { 61 #clock-cells = <0>; 62 compatible = "st,stm32-hse-clock"; 63 status = "disabled"; 64 }; 65 66 clk_hsi: clk-hsi { 67 #clock-cells = <0>; 68 compatible = "st,stm32h7-hsi-clock"; 69 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */ 70 clock-frequency = <DT_FREQ_M(64)>; 71 status = "disabled"; 72 }; 73 74 clk_hsi48: clk-hsi48 { 75 #clock-cells = <0>; 76 compatible = "fixed-clock"; 77 clock-frequency = <DT_FREQ_M(48)>; 78 status = "disabled"; 79 }; 80 81 clk_csi: clk-csi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <DT_FREQ_M(4)>; 85 status = "disabled"; 86 }; 87 88 clk_lse: clk-lse { 89 #clock-cells = <0>; 90 compatible = "st,stm32-lse-clock"; 91 clock-frequency = <32768>; 92 driving-capability = <0>; 93 status = "disabled"; 94 }; 95 96 clk_lsi: clk-lsi { 97 #clock-cells = <0>; 98 compatible = "fixed-clock"; 99 clock-frequency = <DT_FREQ_K(32)>; 100 status = "disabled"; 101 }; 102 103 pll: pll@0 { 104 #clock-cells = <0>; 105 compatible = "st,stm32h7-pll-clock"; 106 reg = <0>; 107 status = "disabled"; 108 }; 109 110 pll2: pll@1 { 111 #clock-cells = <0>; 112 compatible = "st,stm32h7-pll-clock"; 113 reg = <1>; 114 status = "disabled"; 115 }; 116 117 pll3: pll@2 { 118 #clock-cells = <0>; 119 compatible = "st,stm32h7-pll-clock"; 120 reg = <2>; 121 status = "disabled"; 122 }; 123 124 perck: perck { 125 #clock-cells = <0>; 126 compatible = "st,stm32-clock-mux"; 127 status = "disabled"; 128 }; 129 }; 130 131 mcos { 132 mco1: mco1 { 133 compatible = "st,stm32-clock-mco"; 134 status = "disabled"; 135 }; 136 137 mco2: mco2 { 138 compatible = "st,stm32-clock-mco"; 139 status = "disabled"; 140 }; 141 }; 142 143 soc { 144 flash: flash-controller@52002000 { 145 compatible = "st,stm32-flash-controller", "st,stm32h7-flash-controller"; 146 reg = <0x52002000 0x400>; 147 interrupts = <4 0>; 148 149 #address-cells = <1>; 150 #size-cells = <1>; 151 }; 152 153 rcc: rcc@58024400 { 154 compatible = "st,stm32h7-rcc"; 155 #clock-cells = <2>; 156 reg = <0x58024400 0x400>; 157 158 rctl: reset-controller { 159 compatible = "st,stm32-rcc-rctl"; 160 #reset-cells = <1>; 161 }; 162 }; 163 164 exti: interrupt-controller@58000000 { 165 compatible = "st,stm32-exti"; 166 interrupt-controller; 167 #interrupt-cells = <1>; 168 #address-cells = <1>; 169 reg = <0x58000000 0x400>; 170 num-lines = <16>; 171 interrupts = <6 0>, <7 0>, <8 0>, <9 0>, 172 <10 0>, <23 0>, <40 0>; 173 interrupt-names = "line0", "line1", "line2", "line3", 174 "line4", "line5-9", "line10-15"; 175 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 176 <4 1>, <5 5>, <10 6>; 177 }; 178 179 pinctrl: pin-controller@58020000 { 180 compatible = "st,stm32-pinctrl"; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 reg = <0x58020000 0x2400>; 184 185 gpioa: gpio@58020000 { 186 compatible = "st,stm32-gpio"; 187 gpio-controller; 188 #gpio-cells = <2>; 189 reg = <0x58020000 0x400>; 190 clocks = <&rcc STM32_CLOCK(AHB4, 0U)>; 191 }; 192 193 gpiob: gpio@58020400 { 194 compatible = "st,stm32-gpio"; 195 gpio-controller; 196 #gpio-cells = <2>; 197 reg = <0x58020400 0x400>; 198 clocks = <&rcc STM32_CLOCK(AHB4, 1U)>; 199 }; 200 201 gpioc: gpio@58020800 { 202 compatible = "st,stm32-gpio"; 203 gpio-controller; 204 #gpio-cells = <2>; 205 reg = <0x58020800 0x400>; 206 clocks = <&rcc STM32_CLOCK(AHB4, 2U)>; 207 }; 208 209 gpiod: gpio@58020C00 { 210 compatible = "st,stm32-gpio"; 211 gpio-controller; 212 #gpio-cells = <2>; 213 reg = <0x58020C00 0x400>; 214 clocks = <&rcc STM32_CLOCK(AHB4, 3U)>; 215 }; 216 217 gpioe: gpio@58021000 { 218 compatible = "st,stm32-gpio"; 219 gpio-controller; 220 #gpio-cells = <2>; 221 reg = <0x58021000 0x400>; 222 clocks = <&rcc STM32_CLOCK(AHB4, 4U)>; 223 }; 224 225 gpiof: gpio@58021400 { 226 compatible = "st,stm32-gpio"; 227 gpio-controller; 228 #gpio-cells = <2>; 229 reg = <0x58021400 0x400>; 230 clocks = <&rcc STM32_CLOCK(AHB4, 5U)>; 231 }; 232 233 gpiog: gpio@58021800 { 234 compatible = "st,stm32-gpio"; 235 gpio-controller; 236 #gpio-cells = <2>; 237 reg = <0x58021800 0x400>; 238 clocks = <&rcc STM32_CLOCK(AHB4, 6U)>; 239 }; 240 241 gpioh: gpio@58021C00 { 242 compatible = "st,stm32-gpio"; 243 gpio-controller; 244 #gpio-cells = <2>; 245 reg = <0x58021C00 0x400>; 246 clocks = <&rcc STM32_CLOCK(AHB4, 7U)>; 247 }; 248 249 gpioi: gpio@58022000 { 250 compatible = "st,stm32-gpio"; 251 gpio-controller; 252 #gpio-cells = <2>; 253 reg = <0x58022000 0x400>; 254 clocks = <&rcc STM32_CLOCK(AHB4, 8U)>; 255 }; 256 257 gpioj: gpio@58022400 { 258 compatible = "st,stm32-gpio"; 259 gpio-controller; 260 #gpio-cells = <2>; 261 reg = <0x58022400 0x400>; 262 clocks = <&rcc STM32_CLOCK(AHB4, 9U)>; 263 }; 264 265 gpiok: gpio@58022800 { 266 compatible = "st,stm32-gpio"; 267 gpio-controller; 268 #gpio-cells = <2>; 269 reg = <0x58022800 0x400>; 270 clocks = <&rcc STM32_CLOCK(AHB4, 10U)>; 271 }; 272 }; 273 274 iwdg: iwdg1: watchdog@58004800 { 275 compatible = "st,stm32-watchdog"; 276 reg = <0x58004800 0x400>; 277 status = "disabled"; 278 }; 279 280 wwdg: wwdg1: watchdog@50003000 { 281 compatible = "st,stm32-window-watchdog"; 282 reg = <0x50003000 0x1000>; 283 clocks = <&rcc STM32_CLOCK(APB3, 6U)>; 284 interrupts = <0 7>; 285 status = "disabled"; 286 }; 287 288 usart1: serial@40011000 { 289 compatible = "st,stm32-usart", "st,stm32-uart"; 290 reg = <0x40011000 0x400>; 291 clocks = <&rcc STM32_CLOCK(APB2, 4U)>; 292 resets = <&rctl STM32_RESET(APB2, 4U)>; 293 interrupts = <37 0>; 294 status = "disabled"; 295 }; 296 usart2: serial@40004400 { 297 compatible = "st,stm32-usart", "st,stm32-uart"; 298 reg = <0x40004400 0x400>; 299 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 300 resets = <&rctl STM32_RESET(APB1L, 17U)>; 301 interrupts = <38 0>; 302 status = "disabled"; 303 }; 304 usart3: serial@40004800 { 305 compatible = "st,stm32-usart", "st,stm32-uart"; 306 reg = <0x40004800 0x400>; 307 clocks = <&rcc STM32_CLOCK(APB1, 18U)>; 308 resets = <&rctl STM32_RESET(APB1L, 18U)>; 309 interrupts = <39 0>; 310 status = "disabled"; 311 }; 312 uart4: serial@40004c00 { 313 compatible ="st,stm32-uart"; 314 reg = <0x40004c00 0x400>; 315 clocks = <&rcc STM32_CLOCK(APB1, 19U)>; 316 resets = <&rctl STM32_RESET(APB1L, 19U)>; 317 interrupts = <52 0>; 318 status = "disabled"; 319 }; 320 uart5: serial@40005000 { 321 compatible = "st,stm32-uart"; 322 reg = <0x40005000 0x400>; 323 clocks = <&rcc STM32_CLOCK(APB1, 20U)>; 324 resets = <&rctl STM32_RESET(APB1L, 20U)>; 325 interrupts = <53 0>; 326 status = "disabled"; 327 }; 328 usart6: serial@40011400 { 329 compatible = "st,stm32-usart", "st,stm32-uart"; 330 reg = <0x40011400 0x400>; 331 clocks = <&rcc STM32_CLOCK(APB2, 5U)>; 332 resets = <&rctl STM32_RESET(APB2, 5U)>; 333 interrupts = <71 0>; 334 status = "disabled"; 335 }; 336 uart7: serial@40007800 { 337 compatible = "st,stm32-uart"; 338 reg = <0x40007800 0x400>; 339 clocks = <&rcc STM32_CLOCK(APB1, 30U)>; 340 resets = <&rctl STM32_RESET(APB1L, 30U)>; 341 interrupts = <82 0>; 342 status = "disabled"; 343 }; 344 uart8: serial@40007c00 { 345 compatible = "st,stm32-uart"; 346 reg = <0x40007c00 0x400>; 347 clocks = <&rcc STM32_CLOCK(APB1, 31U)>; 348 resets = <&rctl STM32_RESET(APB1L, 31U)>; 349 interrupts = <83 0>; 350 status = "disabled"; 351 }; 352 353 lpuart1: serial@58000c00 { 354 compatible = "st,stm32-lpuart", "st,stm32-uart"; 355 reg = <0x58000c00 0x400>; 356 clocks = <&rcc STM32_CLOCK(APB4, 3U)>; 357 resets = <&rctl STM32_RESET(APB4, 3U)>; 358 interrupts = <142 0>; 359 status = "disabled"; 360 }; 361 362 rtc: rtc@58004000 { 363 compatible = "st,stm32-rtc"; 364 reg = <0x58004000 0x400>; 365 interrupts = <41 0>; 366 clocks = <&rcc STM32_CLOCK(APB4, 16U)>; 367 prescaler = <32768>; 368 alarms-count = <2>; 369 alrm-exti-line = <17>; 370 status = "disabled"; 371 }; 372 373 i2c1: i2c@40005400 { 374 compatible = "st,stm32-i2c-v2"; 375 clock-frequency = <I2C_BITRATE_STANDARD>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 reg = <0x40005400 0x400>; 379 clocks = <&rcc STM32_CLOCK(APB1, 21U)>; 380 interrupts = <31 0>, <32 0>; 381 interrupt-names = "event", "error"; 382 status = "disabled"; 383 }; 384 385 i2c2: i2c@40005800 { 386 compatible = "st,stm32-i2c-v2"; 387 clock-frequency = <I2C_BITRATE_STANDARD>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 reg = <0x40005800 0x400>; 391 clocks = <&rcc STM32_CLOCK(APB1, 22U)>; 392 interrupts = <33 0>, <34 0>; 393 interrupt-names = "event", "error"; 394 status = "disabled"; 395 }; 396 397 i2c3: i2c@40005c00 { 398 compatible = "st,stm32-i2c-v2"; 399 clock-frequency = <I2C_BITRATE_STANDARD>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 reg = <0x40005c00 0x400>; 403 clocks = <&rcc STM32_CLOCK(APB1, 23U)>; 404 interrupts = <72 0>, <73 0>; 405 interrupt-names = "event", "error"; 406 status = "disabled"; 407 }; 408 409 i2c4: i2c@58001c00 { 410 compatible = "st,stm32-i2c-v2"; 411 clock-frequency = <I2C_BITRATE_STANDARD>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 reg = <0x58001c00 0x400>; 415 clocks = <&rcc STM32_CLOCK(APB4, 7U)>; 416 interrupts = <95 0>, <96 0>; 417 interrupt-names = "event", "error"; 418 status = "disabled"; 419 }; 420 421 spi1: spi@40013000 { 422 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 reg = <0x40013000 0x400>; 426 clocks = <&rcc STM32_CLOCK(APB2, 12U)>, 427 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; 428 interrupts = <35 0>; 429 status = "disabled"; 430 }; 431 432 spi2: spi@40003800 { 433 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 reg = <0x40003800 0x400>; 437 clocks = <&rcc STM32_CLOCK(APB1, 14U)>, 438 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; 439 interrupts = <36 0>; 440 status = "disabled"; 441 }; 442 443 spi3: spi@40003c00 { 444 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 reg = <0x40003c00 0x400>; 448 clocks = <&rcc STM32_CLOCK(APB1, 15U)>, 449 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; 450 interrupts = <51 0>; 451 status = "disabled"; 452 }; 453 454 spi4: spi@40013400 { 455 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 reg = <0x40013400 0x400>; 459 clocks = <&rcc STM32_CLOCK(APB2, 13U)>; 460 interrupts = <84 0>; 461 status = "disabled"; 462 }; 463 464 spi5: spi@40015000 { 465 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 reg = <0x40015000 0x400>; 469 clocks = <&rcc STM32_CLOCK(APB2, 20U)>; 470 interrupts = <85 0>; 471 status = "disabled"; 472 }; 473 474 spi6: spi@58001400 { 475 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 reg = <0x58001400 0x400>; 479 clocks = <&rcc STM32_CLOCK(APB4, 5U)>; 480 interrupts = <86 0>; 481 status = "disabled"; 482 }; 483 484 i2s1: i2s@40013000 { 485 compatible = "st,stm32h7-i2s", "st,stm32-i2s"; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 reg = <0x40013000 0x400>; 489 clocks = <&rcc STM32_CLOCK(APB2, 12U)>, 490 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; 491 dmas = <&dmamux1 0 38 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH) 492 &dmamux1 1 37 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>; 493 dma-names = "tx", "rx"; 494 interrupts = <35 3>; 495 status = "disabled"; 496 }; 497 498 i2s2: i2s@40003800 { 499 compatible = "st,stm32h7-i2s", "st,stm32-i2s"; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 reg = <0x40003800 0x400>; 503 clocks = <&rcc STM32_CLOCK(APB1, 14U)>, 504 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; 505 dmas = <&dmamux1 0 40 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH) 506 &dmamux1 1 39 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>; 507 dma-names = "tx", "rx"; 508 interrupts = <36 0>; 509 status = "disabled"; 510 }; 511 512 i2s3: i2s@40003c00 { 513 compatible = "st,stm32h7-i2s", "st,stm32-i2s"; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 reg = <0x40003c00 0x400>; 517 clocks = <&rcc STM32_CLOCK(APB1, 15U)>, 518 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; 519 dmas = <&dmamux1 0 62 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH) 520 &dmamux1 1 61 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>; 521 dma-names = "tx", "rx"; 522 interrupts = <51 0>; 523 status = "disabled"; 524 }; 525 526 fdcan1: can@4000a000 { 527 compatible = "st,stm32h7-fdcan"; 528 reg = <0x4000a000 0x400>, <0x4000ac00 0x350>; 529 reg-names = "m_can", "message_ram"; 530 clocks = <&rcc STM32_CLOCK(APB1_2, 8U)>; 531 interrupts = <19 0>, <21 0>, <63 0>; 532 interrupt-names = "int0", "int1", "calib"; 533 bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; 534 status = "disabled"; 535 }; 536 537 fdcan2: can@4000a400 { 538 compatible = "st,stm32h7-fdcan"; 539 reg = <0x4000a400 0x400>, <0x4000ac00 0x6a0>; 540 reg-names = "m_can", "message_ram"; 541 clocks = <&rcc STM32_CLOCK(APB1_2, 8U)>; 542 interrupts = <20 0>, <22 0>, <63 0>; 543 interrupt-names = "int0", "int1", "calib"; 544 bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>; 545 status = "disabled"; 546 }; 547 548 timers1: timers@40010000 { 549 compatible = "st,stm32-timers"; 550 reg = <0x40010000 0x400>; 551 clocks = <&rcc STM32_CLOCK(APB2, 0U)>; 552 resets = <&rctl STM32_RESET(APB2, 0U)>; 553 interrupts = <24 0>, <25 0>, <26 0>, <27 0>; 554 interrupt-names = "brk", "up", "trgcom", "cc"; 555 st,prescaler = <0>; 556 status = "disabled"; 557 558 pwm { 559 compatible = "st,stm32-pwm"; 560 status = "disabled"; 561 #pwm-cells = <3>; 562 }; 563 }; 564 565 timers2: timers@40000000 { 566 compatible = "st,stm32-timers"; 567 reg = <0x40000000 0x400>; 568 clocks = <&rcc STM32_CLOCK(APB1, 0U)>; 569 resets = <&rctl STM32_RESET(APB1L, 0U)>; 570 interrupts = <28 0>; 571 interrupt-names = "global"; 572 st,prescaler = <0>; 573 status = "disabled"; 574 575 pwm { 576 compatible = "st,stm32-pwm"; 577 status = "disabled"; 578 #pwm-cells = <3>; 579 }; 580 581 counter { 582 compatible = "st,stm32-counter"; 583 status = "disabled"; 584 }; 585 }; 586 587 timers3: timers@40000400 { 588 compatible = "st,stm32-timers"; 589 reg = <0x40000400 0x400>; 590 clocks = <&rcc STM32_CLOCK(APB1, 1U)>; 591 resets = <&rctl STM32_RESET(APB1L, 1U)>; 592 interrupts = <29 0>; 593 interrupt-names = "global"; 594 st,prescaler = <0>; 595 status = "disabled"; 596 597 pwm { 598 compatible = "st,stm32-pwm"; 599 status = "disabled"; 600 #pwm-cells = <3>; 601 }; 602 603 counter { 604 compatible = "st,stm32-counter"; 605 status = "disabled"; 606 }; 607 }; 608 609 timers4: timers@40000800 { 610 compatible = "st,stm32-timers"; 611 reg = <0x40000800 0x400>; 612 clocks = <&rcc STM32_CLOCK(APB1, 2U)>; 613 resets = <&rctl STM32_RESET(APB1L, 2U)>; 614 interrupts = <30 0>; 615 interrupt-names = "global"; 616 st,prescaler = <0>; 617 status = "disabled"; 618 619 pwm { 620 compatible = "st,stm32-pwm"; 621 status = "disabled"; 622 #pwm-cells = <3>; 623 }; 624 625 counter { 626 compatible = "st,stm32-counter"; 627 status = "disabled"; 628 }; 629 }; 630 631 timers5: timers@40000c00 { 632 compatible = "st,stm32-timers"; 633 reg = <0x40000c00 0x400>; 634 clocks = <&rcc STM32_CLOCK(APB1, 3U)>; 635 resets = <&rctl STM32_RESET(APB1L, 3U)>; 636 interrupts = <50 0>; 637 interrupt-names = "global"; 638 st,prescaler = <0>; 639 status = "disabled"; 640 641 pwm { 642 compatible = "st,stm32-pwm"; 643 status = "disabled"; 644 #pwm-cells = <3>; 645 }; 646 647 counter { 648 compatible = "st,stm32-counter"; 649 status = "disabled"; 650 }; 651 }; 652 653 timers6: timers@40001000 { 654 compatible = "st,stm32-timers"; 655 reg = <0x40001000 0x400>; 656 clocks = <&rcc STM32_CLOCK(APB1, 4U)>; 657 resets = <&rctl STM32_RESET(APB1L, 4U)>; 658 interrupts = <54 0>; 659 interrupt-names = "global"; 660 st,prescaler = <0>; 661 status = "disabled"; 662 663 counter { 664 compatible = "st,stm32-counter"; 665 status = "disabled"; 666 }; 667 }; 668 669 timers7: timers@40001400 { 670 compatible = "st,stm32-timers"; 671 reg = <0x40001400 0x400>; 672 clocks = <&rcc STM32_CLOCK(APB1, 5U)>; 673 resets = <&rctl STM32_RESET(APB1L, 5U)>; 674 interrupts = <55 0>; 675 interrupt-names = "global"; 676 st,prescaler = <0>; 677 status = "disabled"; 678 679 counter { 680 compatible = "st,stm32-counter"; 681 status = "disabled"; 682 }; 683 }; 684 685 timers8: timers@40010400 { 686 compatible = "st,stm32-timers"; 687 reg = <0x40010400 0x400>; 688 clocks = <&rcc STM32_CLOCK(APB2, 1U)>; 689 resets = <&rctl STM32_RESET(APB2, 1U)>; 690 interrupts = <43 0>, <44 0>, <45 0>, <46 0>; 691 interrupt-names = "brk", "up", "trgcom", "cc"; 692 st,prescaler = <0>; 693 status = "disabled"; 694 695 pwm { 696 compatible = "st,stm32-pwm"; 697 status = "disabled"; 698 #pwm-cells = <3>; 699 }; 700 }; 701 702 timers12: timers@40001800 { 703 compatible = "st,stm32-timers"; 704 reg = <0x40001800 0x400>; 705 clocks = <&rcc STM32_CLOCK(APB1, 6U)>; 706 resets = <&rctl STM32_RESET(APB1L, 6U)>; 707 interrupts = <43 0>; 708 interrupt-names = "global"; 709 st,prescaler = <0>; 710 status = "disabled"; 711 712 pwm { 713 compatible = "st,stm32-pwm"; 714 status = "disabled"; 715 #pwm-cells = <3>; 716 }; 717 718 counter { 719 compatible = "st,stm32-counter"; 720 status = "disabled"; 721 }; 722 }; 723 724 timers13: timers@40001c00 { 725 compatible = "st,stm32-timers"; 726 reg = <0x40001c00 0x400>; 727 clocks = <&rcc STM32_CLOCK(APB1, 7U)>; 728 resets = <&rctl STM32_RESET(APB1L, 7U)>; 729 interrupts = <44 0>; 730 interrupt-names = "global"; 731 st,prescaler = <0>; 732 status = "disabled"; 733 734 pwm { 735 compatible = "st,stm32-pwm"; 736 status = "disabled"; 737 #pwm-cells = <3>; 738 }; 739 740 counter { 741 compatible = "st,stm32-counter"; 742 status = "disabled"; 743 }; 744 }; 745 746 timers14: timers@40002000 { 747 compatible = "st,stm32-timers"; 748 reg = <0x40002000 0x400>; 749 clocks = <&rcc STM32_CLOCK(APB1, 8U)>; 750 resets = <&rctl STM32_RESET(APB1L, 8U)>; 751 interrupts = <45 0>; 752 interrupt-names = "global"; 753 st,prescaler = <0>; 754 status = "disabled"; 755 756 pwm { 757 compatible = "st,stm32-pwm"; 758 status = "disabled"; 759 #pwm-cells = <3>; 760 }; 761 762 counter { 763 compatible = "st,stm32-counter"; 764 status = "disabled"; 765 }; 766 }; 767 768 timers15: timers@40014000 { 769 compatible = "st,stm32-timers"; 770 reg = <0x40014000 0x400>; 771 clocks = <&rcc STM32_CLOCK(APB2, 16U)>; 772 resets = <&rctl STM32_RESET(APB2, 16U)>; 773 interrupts = <116 0>; 774 interrupt-names = "global"; 775 st,prescaler = <0>; 776 status = "disabled"; 777 778 pwm { 779 compatible = "st,stm32-pwm"; 780 status = "disabled"; 781 #pwm-cells = <3>; 782 }; 783 784 counter { 785 compatible = "st,stm32-counter"; 786 status = "disabled"; 787 }; 788 }; 789 790 timers16: timers@40014400 { 791 compatible = "st,stm32-timers"; 792 reg = <0x40014400 0x400>; 793 clocks = <&rcc STM32_CLOCK(APB2, 17U)>; 794 resets = <&rctl STM32_RESET(APB2, 17U)>; 795 interrupts = <117 0>; 796 interrupt-names = "global"; 797 st,prescaler = <0>; 798 status = "disabled"; 799 800 pwm { 801 compatible = "st,stm32-pwm"; 802 status = "disabled"; 803 #pwm-cells = <3>; 804 }; 805 806 counter { 807 compatible = "st,stm32-counter"; 808 status = "disabled"; 809 }; 810 }; 811 812 timers17: timers@40014800 { 813 compatible = "st,stm32-timers"; 814 reg = <0x40014800 0x400>; 815 clocks = <&rcc STM32_CLOCK(APB2, 18U)>; 816 resets = <&rctl STM32_RESET(APB2, 18U)>; 817 interrupts = <118 0>; 818 interrupt-names = "global"; 819 st,prescaler = <0>; 820 status = "disabled"; 821 822 pwm { 823 compatible = "st,stm32-pwm"; 824 status = "disabled"; 825 #pwm-cells = <3>; 826 }; 827 828 counter { 829 compatible = "st,stm32-counter"; 830 status = "disabled"; 831 }; 832 }; 833 834 lptim1: timers@40002400 { 835 compatible = "st,stm32-lptim"; 836 clocks = <&rcc STM32_CLOCK(APB1, 9U)>; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 reg = <0x40002400 0x400>; 840 interrupts = <93 1>; 841 interrupt-names = "wakeup"; 842 status = "disabled"; 843 }; 844 845 /* 846 * For devices STM32H742, H743, H750 & H753, revision Y only, 847 * resolution 14 and 12 shall be replaced, respectively, by 848 * STM32_ADC_RES(14, 0x01) and STM32_ADC_RES(12, 0x02) 849 * for all ADCs 850 * See RM0433 for more details 851 */ 852 adc1: adc@40022000 { 853 compatible = "st,stm32-adc"; 854 reg = <0x40022000 0x400>; 855 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; 856 interrupts = <18 0>; 857 status = "disabled"; 858 #io-channel-cells = <1>; 859 resolutions = <STM32_ADC_RES(16, 0x00) 860 STM32_ADC_RES(14, 0x05) 861 STM32_ADC_RES(12, 0x06) 862 STM32_ADC_RES(10, 0x03) 863 STM32_ADC_RES(8, 0x07)>; 864 sampling-times = <2 3 9 17 33 65 388 811>; 865 st,adc-sequencer = "FULLY_CONFIGURABLE"; 866 st,adc-oversampler = "OVERSAMPLER_EXTENDED"; 867 }; 868 869 adc2: adc@40022100 { 870 compatible = "st,stm32-adc"; 871 reg = <0x40022100 0x400>; 872 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; 873 interrupts = <18 0>; 874 status = "disabled"; 875 #io-channel-cells = <1>; 876 resolutions = <STM32_ADC_RES(16, 0x00) 877 STM32_ADC_RES(14, 0x05) 878 STM32_ADC_RES(12, 0x06) 879 STM32_ADC_RES(10, 0x03) 880 STM32_ADC_RES(8, 0x07)>; 881 sampling-times = <2 3 9 17 33 65 388 811>; 882 st,adc-sequencer = "FULLY_CONFIGURABLE"; 883 st,adc-oversampler = "OVERSAMPLER_EXTENDED"; 884 }; 885 886 /* dual mode: adc1 and adc2 coupled */ 887 adc1_2: adc@40022300 { 888 compatible = "st,stm32-adc"; 889 reg = <0x40022300 0x400>; 890 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; 891 interrupts = <18 0>; 892 status = "disabled"; 893 #io-channel-cells = <1>; 894 resolutions = <STM32_ADC_RES(16, 0x00) 895 STM32_ADC_RES(14, 0x05) 896 STM32_ADC_RES(12, 0x06) 897 STM32_ADC_RES(10, 0x03) 898 STM32_ADC_RES(8, 0x07)>; 899 sampling-times = <2 3 9 17 33 65 388 811>; 900 st,adc-sequencer = "FULLY_CONFIGURABLE"; 901 st,adc-oversampler = "OVERSAMPLER_EXTENDED"; 902 }; 903 904 adc3: adc@58026000 { 905 compatible = "st,stm32-adc"; 906 reg = <0x58026000 0x400>; 907 clocks = <&rcc STM32_CLOCK(AHB4, 24U)>; 908 interrupts = <127 0>; 909 status = "disabled"; 910 #io-channel-cells = <1>; 911 resolutions = <STM32_ADC_RES(16, 0x00) 912 STM32_ADC_RES(14, 0x05) 913 STM32_ADC_RES(12, 0x06) 914 STM32_ADC_RES(10, 0x03) 915 STM32_ADC_RES(8, 0x07)>; 916 sampling-times = <2 3 9 17 33 65 388 811>; 917 st,adc-sequencer = "FULLY_CONFIGURABLE"; 918 st,adc-oversampler = "OVERSAMPLER_EXTENDED"; 919 }; 920 921 dac1: dac@40007400 { 922 compatible = "st,stm32-dac"; 923 reg = <0x40007400 0x400>; 924 clocks = <&rcc STM32_CLOCK(APB1, 29U)>; 925 status = "disabled"; 926 #io-channel-cells = <1>; 927 }; 928 929 dma1: dma@40020000 { 930 compatible = "st,stm32-dma-v1"; 931 #dma-cells = <4>; 932 reg = <0x40020000 0x400>; 933 interrupts = <11 0>, <12 0>, <13 0>, <14 0>, <15 0>, <16 0>, 934 <17 0>, <47 0>; 935 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; 936 st,mem2mem; 937 dma-offset = <0>; 938 dma-requests = <8>; 939 status = "disabled"; 940 }; 941 942 dma2: dma@40020400 { 943 compatible = "st,stm32-dma-v1"; 944 #dma-cells = <4>; 945 reg = <0x40020400 0x400>; 946 interrupts = <56 0>, <57 0>, <58 0>, <59 0>, <60 0>, <68 0>, 947 <69 0>, <70 0>; 948 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; 949 st,mem2mem; 950 dma-offset = <8>; 951 dma-requests = <8>; 952 status = "disabled"; 953 }; 954 955 bdma1: bdma@58025400 { 956 compatible = "st,stm32-bdma"; 957 #dma-cells = <4>; 958 reg = <0x58025400 0x400>; 959 interrupts = <129 0>, <130 0>, <131 0>, <132 0>, <133 0>, <134 0>, 960 <135 0>, <136 0>; 961 clocks = <&rcc STM32_CLOCK(AHB4, 21U)>; 962 st,mem2mem; 963 dma-offset = <0>; 964 dma-requests = <8>; 965 status = "disabled"; 966 }; 967 968 dmamux1: dmamux@40020800 { 969 compatible = "st,stm32-dmamux"; 970 #dma-cells = <3>; 971 reg = <0x40020800 0x400>; 972 interrupts = <102 0>; 973 /* dmamux1 has no dedicated clock, so we enable dma1 clock */ 974 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; 975 dma-channels = <16>; 976 dma-generators = <8>; 977 status = "disabled"; 978 /* 979 * dma-requests is different among h7 socs, 980 * so we set in specific dtsi files 981 */ 982 }; 983 984 dmamux2: dmamux@58025800 { 985 compatible = "st,stm32-dmamux"; 986 #dma-cells = <3>; 987 reg = <0x58025800 0x400>; 988 interrupts = <128 0>; 989 /* dmamux2 has no dedicated clock, so we enable bdma clock */ 990 clocks = <&rcc STM32_CLOCK(AHB4, 21U)>; 991 dma-channels = <8>; 992 dma-generators = <8>; 993 status = "disabled"; 994 /* 995 * dma-requests is different among h7 socs, 996 * so we set in specific dtsi files 997 */ 998 }; 999 1000 rng: rng@48021800 { 1001 compatible = "st,stm32-rng"; 1002 reg = <0x48021800 0x400>; 1003 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; 1004 interrupts = <80 0>; 1005 status = "disabled"; 1006 }; 1007 1008 sdmmc1: sdmmc@52007000 { 1009 compatible = "st,stm32-sdmmc"; 1010 reg = <0x52007000 0x400>; 1011 clocks = <&rcc STM32_CLOCK(AHB3, 16U)>, 1012 <&rcc STM32_SRC_PLL1_Q SDMMC_SEL(0)>; 1013 resets = <&rctl STM32_RESET(AHB3, 16U)>; 1014 interrupts = <49 0>; 1015 status = "disabled"; 1016 }; 1017 1018 sdmmc2: sdmmc@48022400 { 1019 compatible = "st,stm32-sdmmc"; 1020 reg = <0x48022400 0x400>; 1021 clocks = <&rcc STM32_CLOCK(AHB2, 9U)>, 1022 <&rcc STM32_SRC_PLL1_Q SDMMC_SEL(0)>; 1023 resets = <&rctl STM32_RESET(AHB2, 9U)>; 1024 interrupts = <124 0>; 1025 status = "disabled"; 1026 }; 1027 1028 mac: ethernet@40028000 { 1029 compatible = "st,stm32h7-ethernet", "st,stm32-ethernet"; 1030 reg = <0x40028000 0x8000>; 1031 interrupts = <61 0>; 1032 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; 1033 clocks = <&rcc STM32_CLOCK(AHB1, 15U)>, 1034 <&rcc STM32_CLOCK(AHB1, 16U)>, 1035 <&rcc STM32_CLOCK(AHB1, 17U)>; 1036 status = "disabled"; 1037 1038 mdio: mdio { 1039 compatible = "st,stm32-mdio"; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 status = "disabled"; 1043 }; 1044 }; 1045 1046 fmc: memory-controller@52004000 { 1047 compatible = "st,stm32h7-fmc"; 1048 reg = <0x52004000 0x400>; 1049 clocks = <&rcc STM32_CLOCK(AHB3, 12U)>; 1050 status = "disabled"; 1051 1052 sdram: sdram { 1053 compatible = "st,stm32-fmc-sdram"; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 status = "disabled"; 1057 }; 1058 }; 1059 1060 backup_sram: memory@38800000 { 1061 compatible = "zephyr,memory-region", "st,stm32-backup-sram"; 1062 reg = <0x38800000 DT_SIZE_K(4)>; 1063 clocks = <&rcc STM32_CLOCK(AHB4, 28U)>; 1064 zephyr,memory-region = "BACKUP_SRAM"; 1065 status = "disabled"; 1066 }; 1067 1068 quadspi: quadspi@52005000 { 1069 compatible = "st,stm32-qspi"; 1070 #address-cells = <0x1>; 1071 #size-cells = <0x0>; 1072 reg = <0x52005000 0x34>; 1073 interrupts = <92 0>; 1074 clocks = <&rcc STM32_CLOCK(AHB3, 14U)>; 1075 status = "disabled"; 1076 }; 1077 1078 dcmi: dcmi@48020000 { 1079 compatible = "st,stm32-dcmi"; 1080 reg = <0x48020000 0x400>; 1081 interrupts = <78 0>; 1082 interrupt-names = "dcmi"; 1083 clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; 1084 status = "disabled"; 1085 }; 1086 }; 1087 1088 die_temp: dietemp { 1089 compatible = "st,stm32-temp-cal"; 1090 ts-cal1-addr = <0x1FF1E820>; 1091 ts-cal2-addr = <0x1FF1E840>; 1092 ts-cal1-temp = <30>; 1093 ts-cal2-temp = <110>; 1094 ts-cal-vrefanalog = <3300>; 1095 ts-cal-resolution = <16>; 1096 io-channels = <&adc3 18>; 1097 status = "disabled"; 1098 }; 1099 1100 vbat: vbat { 1101 compatible = "st,stm32-vbat"; 1102 ratio = <4>; 1103 status = "disabled"; 1104 }; 1105 1106 vref: vref { 1107 compatible = "st,stm32-vref"; 1108 vrefint-cal-addr = <0x1FF1E860>; 1109 vrefint-cal-mv = <3300>; 1110 status = "disabled"; 1111 }; 1112 1113 smbus1: smbus1 { 1114 compatible = "st,stm32-smbus"; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 i2c = <&i2c1>; 1118 status = "disabled"; 1119 }; 1120 1121 smbus2: smbus2 { 1122 compatible = "st,stm32-smbus"; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 i2c = <&i2c2>; 1126 status = "disabled"; 1127 }; 1128 1129 smbus3: smbus3 { 1130 compatible = "st,stm32-smbus"; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 i2c = <&i2c3>; 1134 status = "disabled"; 1135 }; 1136 1137 smbus4: smbus4 { 1138 compatible = "st,stm32-smbus"; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 i2c = <&i2c4>; 1142 status = "disabled"; 1143 }; 1144}; 1145 1146&nvic { 1147 arm,num-irq-priority-bits = <4>; 1148}; 1149
