Lines Matching +full:stm32 +full:- +full:dma +full:- +full:v2
2 * Copyright (c) 2020-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/clock/stm32wl_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/lora/sx126x.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/adc/adc.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32wb_l_reset.h>
18 #include <zephyr/dt-bindings/power/stm32_pwr.h>
24 zephyr,flash-controller = &flash;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-m4";
35 cpu-power-states = <&stop0 &stop1 &stop2>;
38 power-states {
40 compatible = "zephyr,power-state";
41 power-state-name = "suspend-to-idle";
42 substate-id = <1>;
43 min-residency-us = <100>;
46 compatible = "zephyr,power-state";
47 power-state-name = "suspend-to-idle";
48 substate-id = <2>;
49 min-residency-us = <500>;
52 compatible = "zephyr,power-state";
53 power-state-name = "suspend-to-idle";
54 substate-id = <3>;
55 min-residency-us = <900>;
61 compatible = "mmio-sram";
65 clk_hse: clk-hse {
66 #clock-cells = <0>;
67 compatible = "st,stm32wl-hse-clock";
68 /* Expected clock-frequency on the whole series 32MHz */
69 clock-frequency = <DT_FREQ_M(32)>;
73 clk_hsi: clk-hsi {
74 #clock-cells = <0>;
75 compatible = "fixed-clock";
76 clock-frequency = <DT_FREQ_M(16)>;
80 clk_msi: clk-msi {
81 #clock-cells = <0>;
82 compatible = "st,stm32-msi-clock";
83 msi-range = <6>; /* 4MHz (reset value) */
87 clk_lse: clk-lse {
88 #clock-cells = <0>;
89 compatible = "st,stm32-lse-clock";
90 clock-frequency = <32768>;
91 driving-capability = <0>;
95 clk_lsi: clk-lsi {
96 #clock-cells = <0>;
97 compatible = "fixed-clock";
98 clock-frequency = <DT_FREQ_K(32)>;
103 #clock-cells = <0>;
104 compatible = "st,stm32wb-pll-clock";
110 flash: flash-controller@58004000 {
111 compatible = "st,stm32-flash-controller", "st,stm32l4-flash-controller";
115 #address-cells = <1>;
116 #size-cells = <1>;
119 compatible = "st,stm32-nv-flash", "soc-nv-flash";
121 write-block-size = <8>;
122 erase-block-size = <2048>;
124 max-erase-time = <25>;
129 compatible = "st,stm32wl-rcc";
130 #clock-cells = <2>;
133 rctl: reset-controller {
134 compatible = "st,stm32-rcc-rctl";
135 #reset-cells = <1>;
139 exti: interrupt-controller@58000800 {
140 compatible = "st,stm32-exti";
141 interrupt-controller;
142 #interrupt-cells = <1>;
143 #address-cells = <1>;
145 num-lines = <16>;
148 interrupt-names = "line0", "line1", "line2", "line3",
149 "line4", "line5-9", "line10-15";
150 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
154 pinctrl: pin-controller@48000000 {
155 compatible = "st,stm32-pinctrl";
156 #address-cells = <1>;
157 #size-cells = <1>;
161 compatible = "st,stm32-gpio";
162 gpio-controller;
163 #gpio-cells = <2>;
169 compatible = "st,stm32-gpio";
170 gpio-controller;
171 #gpio-cells = <2>;
177 compatible = "st,stm32-gpio";
178 gpio-controller;
179 #gpio-cells = <2>;
185 compatible = "st,stm32-gpio";
186 gpio-controller;
187 #gpio-cells = <2>;
194 compatible = "st,stm32-lptim";
196 #address-cells = <1>;
197 #size-cells = <0>;
200 interrupt-names = "wakeup";
205 compatible = "st,stm32-rtc";
210 alarms-count = <2>;
211 alrm-exti-line = <17>;
221 compatible = "st,stm32-bbram";
222 st,backup-regs = <20>;
228 compatible = "st,stm32-watchdog";
234 compatible = "st,stm32-window-watchdog";
242 compatible = "st,stm32-usart", "st,stm32-uart";
251 compatible = "st,stm32-usart", "st,stm32-uart";
260 compatible = "st,stm32-lpuart", "st,stm32-uart";
265 wakeup-line = <28>;
270 compatible = "st,stm32-i2c-v2";
271 clock-frequency = <I2C_BITRATE_STANDARD>;
272 #address-cells = <1>;
273 #size-cells = <0>;
277 interrupt-names = "event", "error";
282 compatible = "st,stm32-i2c-v2";
283 clock-frequency = <I2C_BITRATE_STANDARD>;
284 #address-cells = <1>;
285 #size-cells = <0>;
289 interrupt-names = "event", "error";
294 compatible = "st,stm32-i2c-v2";
295 clock-frequency = <I2C_BITRATE_STANDARD>;
296 #address-cells = <1>;
297 #size-cells = <0>;
301 interrupt-names = "event", "error";
306 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
307 #address-cells = <1>;
308 #size-cells = <0>;
316 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
317 #address-cells = <1>;
318 #size-cells = <0>;
326 compatible = "st,stm32-spi-subghz", "st,stm32-spi-fifo", "st,stm32-spi";
327 #address-cells = <1>;
328 #size-cells = <0>;
333 use-subghzspi-nss;
336 compatible = "st,stm32wl-subghz-radio";
339 spi-max-frequency = <8000000>;
345 compatible = "st,stm32-adc";
350 #io-channel-cells = <1>;
355 sampling-times = <2 4 8 13 20 40 80 161>;
356 num-sampling-time-common-channels = <2>;
357 st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
358 st,adc-oversampler = "OVERSAMPLER_MINIMAL";
362 compatible = "st,stm32-dac";
366 #io-channel-cells = <1>;
370 compatible = "st,stm32-timers";
375 interrupt-names = "brk", "up", "trgcom", "cc";
380 compatible = "st,stm32-pwm";
382 #pwm-cells = <3>;
387 compatible = "st,stm32-timers";
392 interrupt-names = "global";
397 compatible = "st,stm32-pwm";
399 #pwm-cells = <3>;
403 compatible = "st,stm32-counter";
409 compatible = "st,stm32-timers";
414 interrupt-names = "global";
419 compatible = "st,stm32-pwm";
421 #pwm-cells = <3>;
425 compatible = "st,stm32-counter";
431 compatible = "st,stm32-timers";
436 interrupt-names = "global";
441 compatible = "st,stm32-pwm";
443 #pwm-cells = <3>;
447 compatible = "st,stm32-counter";
453 compatible = "st,stm32-aes";
462 compatible = "st,stm32-rng";
466 health-test-magic = <0x17590abc>;
467 health-test-config = <0xaa74>;
471 dma1: dma@40020000 {
472 compatible = "st,stm32-dma-v2";
473 #dma-cells = <3>;
477 dma-requests = <7>;
478 dma-offset = <0>;
482 dma2: dma@40020400 {
483 compatible = "st,stm32-dma-v2";
484 #dma-cells = <3>;
488 dma-requests = <7>;
489 dma-offset = <7>;
494 compatible = "st,stm32-dmamux";
495 #dma-cells = <3>;
499 dma-channels = <14>;
500 dma-generators = <4>;
501 dma-requests= <38>;
506 compatible = "st,stm32-pwr";
510 wkup-pins-nb = <3>; /* 3 system wake-up pins */
511 wkup-pins-pol;
512 wkup-pins-pupd;
514 #address-cells = <1>;
515 #size-cells = <0>;
517 wkup-pin@1 {
519 wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>;
522 wkup-pin@2 {
524 wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_SRC_0>;
527 wkup-pin@3 {
529 wkup-gpios = <&gpiob 3 STM32_PWR_WKUP_PIN_SRC_0>;
535 compatible = "st,stm32-temp-cal";
536 ts-cal1-addr = <0x1FFF75A8>;
537 ts-cal2-addr = <0x1FFF75C8>;
538 ts-cal1-temp = <30>;
539 ts-cal2-temp = <130>;
540 ts-cal-vrefanalog = <3300>;
541 io-channels = <&adc1 12>;
546 compatible = "st,stm32-vref";
547 vrefint-cal-addr = <0x1FFF75AA>;
548 vrefint-cal-mv = <3300>;
549 io-channels = <&adc1 13>;
554 compatible = "st,stm32-vbat";
556 io-channels = <&adc1 14>;
561 compatible = "st,stm32-smbus";
562 #address-cells = <1>;
563 #size-cells = <0>;
569 compatible = "st,stm32-smbus";
570 #address-cells = <1>;
571 #size-cells = <0>;
577 compatible = "st,stm32-smbus";
578 #address-cells = <1>;
579 #size-cells = <0>;
586 arm,num-irq-priority-bits = <4>;