1/*
2 * Copyright (c) 2020-2024 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <zephyr/dt-bindings/clock/stm32wl_clock.h>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/lora/sx126x.h>
12#include <zephyr/dt-bindings/pwm/pwm.h>
13#include <zephyr/dt-bindings/adc/adc.h>
14#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15#include <zephyr/dt-bindings/dma/stm32_dma.h>
16#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
17#include <zephyr/dt-bindings/reset/stm32wb_l_reset.h>
18#include <zephyr/dt-bindings/power/stm32_pwr.h>
19#include <freq.h>
20
21/ {
22	chosen {
23		zephyr,entropy = &rng;
24		zephyr,flash-controller = &flash;
25	};
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		cpu0: cpu@0 {
32			device_type = "cpu";
33			compatible = "arm,cortex-m4";
34			reg = <0>;
35			cpu-power-states = <&stop0 &stop1 &stop2>;
36		};
37
38		power-states {
39			stop0: state0 {
40				compatible = "zephyr,power-state";
41				power-state-name = "suspend-to-idle";
42				substate-id = <1>;
43				min-residency-us = <100>;
44			};
45			stop1: state1 {
46				compatible = "zephyr,power-state";
47				power-state-name = "suspend-to-idle";
48				substate-id = <2>;
49				min-residency-us = <500>;
50			};
51			stop2: state2 {
52				compatible = "zephyr,power-state";
53				power-state-name = "suspend-to-idle";
54				substate-id = <3>;
55				min-residency-us = <900>;
56			};
57		};
58	};
59
60	sram0: memory@20000000 {
61		compatible = "mmio-sram";
62	};
63
64	clocks {
65		clk_hse: clk-hse {
66			#clock-cells = <0>;
67			compatible = "st,stm32wl-hse-clock";
68			/* Expected clock-frequency on the whole series 32MHz */
69			clock-frequency = <DT_FREQ_M(32)>;
70			status = "disabled";
71		};
72
73		clk_hsi: clk-hsi {
74			#clock-cells = <0>;
75			compatible = "fixed-clock";
76			clock-frequency = <DT_FREQ_M(16)>;
77			status = "disabled";
78		};
79
80		clk_msi: clk-msi {
81			#clock-cells = <0>;
82			compatible = "st,stm32-msi-clock";
83			msi-range = <6>; /* 4MHz (reset value) */
84			status = "disabled";
85		};
86
87		clk_lse: clk-lse {
88			#clock-cells = <0>;
89			compatible = "st,stm32-lse-clock";
90			clock-frequency = <32768>;
91			driving-capability = <0>;
92			status = "disabled";
93		};
94
95		clk_lsi: clk-lsi {
96			#clock-cells = <0>;
97			compatible = "fixed-clock";
98			clock-frequency = <DT_FREQ_K(32)>;
99			status = "disabled";
100		};
101
102		pll: pll {
103			#clock-cells = <0>;
104			compatible = "st,stm32wb-pll-clock";
105			status = "disabled";
106		};
107	};
108
109	soc {
110		flash: flash-controller@58004000 {
111			compatible = "st,stm32-flash-controller", "st,stm32l4-flash-controller";
112			reg = <0x58004000 0x400>;
113			interrupts = <4 0>;
114
115			#address-cells = <1>;
116			#size-cells = <1>;
117
118			flash0: flash@8000000 {
119				compatible = "st,stm32-nv-flash", "soc-nv-flash";
120
121				write-block-size = <8>;
122				erase-block-size = <2048>;
123				/* maximum erase time(ms) for a 2K sector */
124				max-erase-time = <25>;
125			};
126		};
127
128		rcc: rcc@58000000 {
129			compatible = "st,stm32wl-rcc";
130			#clock-cells = <2>;
131			reg = <0x58000000 0x400>;
132
133			rctl: reset-controller {
134				compatible = "st,stm32-rcc-rctl";
135				#reset-cells = <1>;
136			};
137		};
138
139		exti: interrupt-controller@58000800 {
140			compatible = "st,stm32-exti";
141			interrupt-controller;
142			#interrupt-cells = <1>;
143			#address-cells = <1>;
144			reg = <0x58000800 0x400>;
145			num-lines = <16>;
146			interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
147				     <10 0>, <22 0>, <41 0>;
148			interrupt-names = "line0", "line1", "line2", "line3",
149					  "line4", "line5-9", "line10-15";
150			line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
151				      <4 1>, <5 5>, <10 6>;
152		};
153
154		pinctrl: pin-controller@48000000 {
155			compatible = "st,stm32-pinctrl";
156			#address-cells = <1>;
157			#size-cells = <1>;
158			reg = <0x48000000 0x2000>;
159
160			gpioa: gpio@48000000 {
161				compatible = "st,stm32-gpio";
162				gpio-controller;
163				#gpio-cells = <2>;
164				reg = <0x48000000 0x400>;
165				clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
166			};
167
168			gpiob: gpio@48000400 {
169				compatible = "st,stm32-gpio";
170				gpio-controller;
171				#gpio-cells = <2>;
172				reg = <0x48000400 0x400>;
173				clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
174			};
175
176			gpioc: gpio@48000800 {
177				compatible = "st,stm32-gpio";
178				gpio-controller;
179				#gpio-cells = <2>;
180				reg = <0x48000800 0x400>;
181				clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
182			};
183
184			gpioh: gpio@48001c00 {
185				compatible = "st,stm32-gpio";
186				gpio-controller;
187				#gpio-cells = <2>;
188				reg = <0x48001c00 0x400>;
189				clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
190			};
191		};
192
193		lptim1: timers@40007c00 {
194			compatible = "st,stm32-lptim";
195			clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
196			#address-cells = <1>;
197			#size-cells = <0>;
198			reg = <0x40007c00 0x400>;
199			interrupts = <39 1>;
200			interrupt-names = "wakeup";
201			status = "disabled";
202		};
203
204		rtc: rtc@40002800 {
205			compatible = "st,stm32-rtc";
206			reg = <0x40002800 0x400>;
207			interrupts = <42 0>;
208			clocks = <&rcc STM32_CLOCK(APB1, 10U)>;
209			prescaler = <32768>;
210			alarms-count = <2>;
211			alrm-exti-line = <17>;
212			status = "disabled";
213
214			/* In STM32WL, the backup registers are defined as part of the TAMP
215			 * peripheral. This peripheral is not implemented in Zephyr yet, however,
216			 * the reference manual states that tamp_pclk is connected to rtc_pclk.
217			 * It makes sense to have BBRAM instantiated as a child of RTC, so that
218			 * the driver can verify that its parent device (RTC) is ready.
219			 */
220			bbram: backup_regs {
221				compatible = "st,stm32-bbram";
222				st,backup-regs = <20>;
223				status = "disabled";
224			};
225		};
226
227		iwdg: watchdog@40003000 {
228			compatible = "st,stm32-watchdog";
229			reg = <0x40003000 0x400>;
230			status = "disabled";
231		};
232
233		wwdg: watchdog@40002c00 {
234			compatible = "st,stm32-window-watchdog";
235			reg = <0x40002C00 0x400>;
236			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
237			interrupts = <0 7>;
238			status = "disabled";
239		};
240
241		usart1: serial@40013800 {
242			compatible = "st,stm32-usart", "st,stm32-uart";
243			reg = <0x40013800 0x400>;
244			clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
245			resets = <&rctl STM32_RESET(APB2, 14U)>;
246			interrupts = <36 0>;
247			status = "disabled";
248		};
249
250		usart2: serial@40004400 {
251			compatible = "st,stm32-usart", "st,stm32-uart";
252			reg = <0x40004400 0x400>;
253			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
254			resets = <&rctl STM32_RESET(APB1L, 17U)>;
255			interrupts = <37 0>;
256			status = "disabled";
257		};
258
259		lpuart1: serial@40008000 {
260			compatible = "st,stm32-lpuart", "st,stm32-uart";
261			reg = <0x40008000 0x400>;
262			clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>;
263			resets = <&rctl STM32_RESET(APB1H, 0U)>;
264			interrupts = <38 0>;
265			wakeup-line = <28>;
266			status = "disabled";
267		};
268
269		i2c1: i2c@40005400 {
270			compatible = "st,stm32-i2c-v2";
271			clock-frequency = <I2C_BITRATE_STANDARD>;
272			#address-cells = <1>;
273			#size-cells = <0>;
274			reg = <0x40005400 0x400>;
275			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
276			interrupts = <30 0>, <31 0>;
277			interrupt-names = "event", "error";
278			status = "disabled";
279		};
280
281		i2c2: i2c@40005800 {
282			compatible = "st,stm32-i2c-v2";
283			clock-frequency = <I2C_BITRATE_STANDARD>;
284			#address-cells = <1>;
285			#size-cells = <0>;
286			reg = <0x40005800 0x400>;
287			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
288			interrupts = <32 0>, <33 0>;
289			interrupt-names = "event", "error";
290			status = "disabled";
291		};
292
293		i2c3: i2c@40005c00 {
294			compatible = "st,stm32-i2c-v2";
295			clock-frequency = <I2C_BITRATE_STANDARD>;
296			#address-cells = <1>;
297			#size-cells = <0>;
298			reg = <0x40005c00 0x400>;
299			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
300			interrupts = <48 0>, <49 0>;
301			interrupt-names = "event", "error";
302			status = "disabled";
303		};
304
305		spi1: spi@40013000 {
306			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
307			#address-cells = <1>;
308			#size-cells = <0>;
309			reg = <0x40013000 0x400>;
310			interrupts = <34 5>;
311			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
312			status = "disabled";
313		};
314
315		spi2: spi@40003800 {
316			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
317			#address-cells = <1>;
318			#size-cells = <0>;
319			reg = <0x40003800 0x400>;
320			interrupts = <35 5>;
321			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
322			status = "disabled";
323		};
324
325		subghzspi: spi@58010000 {
326			compatible = "st,stm32-spi-subghz", "st,stm32-spi-fifo", "st,stm32-spi";
327			#address-cells = <1>;
328			#size-cells = <0>;
329			reg = <0x58010000 0x400>;
330			interrupts = <44 5>;
331			clocks = <&rcc STM32_CLOCK(APB3, 0U)>;
332			status = "disabled";
333			use-subghzspi-nss;
334
335			radio@0 {
336				compatible = "st,stm32wl-subghz-radio";
337				reg = <0>;
338				interrupts = <50 0>;
339				spi-max-frequency = <8000000>;
340				status = "disabled";
341			};
342		};
343
344		adc1: adc@40012400 {
345			compatible = "st,stm32-adc";
346			reg = <0x40012400 0x400>;
347			clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
348			interrupts = <18 0>;
349			status = "disabled";
350			#io-channel-cells = <1>;
351			resolutions = <STM32_ADC_RES(12, 0x00)
352				       STM32_ADC_RES(10, 0x01)
353				       STM32_ADC_RES(8, 0x02)
354				       STM32_ADC_RES(6, 0x03)>;
355			sampling-times = <2 4 8 13 20 40 80 161>;
356			num-sampling-time-common-channels = <2>;
357			st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
358			st,adc-oversampler = "OVERSAMPLER_MINIMAL";
359		};
360
361		dac1: dac@40007400 {
362			compatible = "st,stm32-dac";
363			reg = <0x40007400 0x400>;
364			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
365			status = "disabled";
366			#io-channel-cells = <1>;
367		};
368
369		timers1: timers@40012c00 {
370			compatible = "st,stm32-timers";
371			reg = <0x40012c00 0x400>;
372			clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
373			resets = <&rctl STM32_RESET(APB2, 11U)>;
374			interrupts = <23 0>, <24 0>, <25 0>, <26 0>;
375			interrupt-names = "brk", "up", "trgcom", "cc";
376			st,prescaler = <0>;
377			status = "disabled";
378
379			pwm {
380				compatible = "st,stm32-pwm";
381				status = "disabled";
382				#pwm-cells = <3>;
383			};
384		};
385
386		timers2: timers@40000000 {
387			compatible = "st,stm32-timers";
388			reg = <0x40000000 0x400>;
389			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
390			resets = <&rctl STM32_RESET(APB1L, 0U)>;
391			interrupts = <27 0>;
392			interrupt-names = "global";
393			st,prescaler = <0>;
394			status = "disabled";
395
396			pwm {
397				compatible = "st,stm32-pwm";
398				status = "disabled";
399				#pwm-cells = <3>;
400			};
401
402			counter {
403				compatible = "st,stm32-counter";
404				status = "disabled";
405			};
406		};
407
408		timers16: timers@40014400 {
409			compatible = "st,stm32-timers";
410			reg = <0x40014400 0x400>;
411			clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
412			resets = <&rctl STM32_RESET(APB2, 17U)>;
413			interrupts = <28 0>;
414			interrupt-names = "global";
415			st,prescaler = <0>;
416			status = "disabled";
417
418			pwm {
419				compatible = "st,stm32-pwm";
420				status = "disabled";
421				#pwm-cells = <3>;
422			};
423
424			counter {
425				compatible = "st,stm32-counter";
426				status = "disabled";
427			};
428		};
429
430		timers17: timers@40014800 {
431			compatible = "st,stm32-timers";
432			reg = <0x40014800 0x400>;
433			clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
434			resets = <&rctl STM32_RESET(APB2, 18U)>;
435			interrupts = <29 0>;
436			interrupt-names = "global";
437			st,prescaler = <0>;
438			status = "disabled";
439
440			pwm {
441				compatible = "st,stm32-pwm";
442				status = "disabled";
443				#pwm-cells = <3>;
444			};
445
446			counter {
447				compatible = "st,stm32-counter";
448				status = "disabled";
449			};
450		};
451
452		aes: aes@58001800 {
453			compatible = "st,stm32-aes";
454			reg = <0x58001800 0x400>;
455			clocks = <&rcc STM32_CLOCK(AHB3, 17U)>;
456			resets = <&rctl STM32_RESET(AHB3, 16U)>;
457			interrupts = <51 0>;
458			status = "disabled";
459		};
460
461		rng: rng@58001000 {
462			compatible = "st,stm32-rng";
463			reg = <0x58001000 0x400>;
464			interrupts = <52 0>;
465			clocks = <&rcc STM32_CLOCK(AHB3, 18U)>;
466			health-test-magic = <0x17590abc>;
467			health-test-config = <0xaa74>;
468			status = "disabled";
469		};
470
471		dma1: dma@40020000 {
472			compatible = "st,stm32-dma-v2";
473			#dma-cells = <3>;
474			reg = <0x40020000 0x400>;
475			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
476			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
477			dma-requests = <7>;
478			dma-offset = <0>;
479			status = "disabled";
480		};
481
482		dma2: dma@40020400 {
483			compatible = "st,stm32-dma-v2";
484			#dma-cells = <3>;
485			reg = <0x40020400 0x400>;
486			interrupts = <54 0 55 0 56 0 57 0 58 0 59 0 60 0>;
487			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
488			dma-requests = <7>;
489			dma-offset = <7>;
490			status = "disabled";
491		};
492
493		dmamux1: dmamux@40020800 {
494			compatible = "st,stm32-dmamux";
495			#dma-cells = <3>;
496			reg = <0x40020800 0x400>;
497			interrupts = <61 0>;
498			clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
499			dma-channels = <14>;
500			dma-generators = <4>;
501			dma-requests= <38>;
502			status = "disabled";
503		};
504
505		pwr: power@58000400 {
506			compatible = "st,stm32-pwr";
507			reg = <0x58000400 0x400>; /* PWR register bank */
508			status = "disabled";
509
510			wkup-pins-nb = <3>; /* 3 system wake-up pins */
511			wkup-pins-pol;
512			wkup-pins-pupd;
513
514			#address-cells = <1>;
515			#size-cells = <0>;
516
517			wkup-pin@1 {
518				reg = <0x1>;
519				wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>;
520			};
521
522			wkup-pin@2 {
523				reg = <0x2>;
524				wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_SRC_0>;
525			};
526
527			wkup-pin@3 {
528				reg = <0x3>;
529				wkup-gpios = <&gpiob 3 STM32_PWR_WKUP_PIN_SRC_0>;
530			};
531		};
532	};
533
534	die_temp: dietemp {
535		compatible = "st,stm32-temp-cal";
536		ts-cal1-addr = <0x1FFF75A8>;
537		ts-cal2-addr = <0x1FFF75C8>;
538		ts-cal1-temp = <30>;
539		ts-cal2-temp = <130>;
540		ts-cal-vrefanalog = <3300>;
541		io-channels = <&adc1 12>;
542		status = "disabled";
543	};
544
545	vref: vref {
546		compatible = "st,stm32-vref";
547		vrefint-cal-addr = <0x1FFF75AA>;
548		vrefint-cal-mv = <3300>;
549		io-channels = <&adc1 13>;
550		status = "disabled";
551	};
552
553	vbat: vbat {
554		compatible = "st,stm32-vbat";
555		ratio = <3>;
556		io-channels = <&adc1 14>;
557		status = "disabled";
558	};
559
560	smbus1: smbus1 {
561		compatible = "st,stm32-smbus";
562		#address-cells = <1>;
563		#size-cells = <0>;
564		i2c = <&i2c1>;
565		status = "disabled";
566	};
567
568	smbus2: smbus2 {
569		compatible = "st,stm32-smbus";
570		#address-cells = <1>;
571		#size-cells = <0>;
572		i2c = <&i2c2>;
573		status = "disabled";
574	};
575
576	smbus3: smbus3 {
577		compatible = "st,stm32-smbus";
578		#address-cells = <1>;
579		#size-cells = <0>;
580		i2c = <&i2c3>;
581		status = "disabled";
582	};
583};
584
585&nvic {
586	arm,num-irq-priority-bits = <4>;
587};
588