1/* 2 * Copyright (c) 2023-2024 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 8#include <arm/armv8-m.dtsi> 9#include <zephyr/dt-bindings/adc/adc.h> 10#include <zephyr/dt-bindings/clock/stm32h5_clock.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/i2c/i2c.h> 13#include <zephyr/dt-bindings/reset/stm32h5_reset.h> 14#include <zephyr/dt-bindings/dma/stm32_dma.h> 15#include <zephyr/dt-bindings/pwm/pwm.h> 16#include <zephyr/dt-bindings/adc/stm32l4_adc.h> 17#include <freq.h> 18 19/ { 20 chosen { 21 zephyr,flash-controller = &flash; 22 zephyr,entropy = &rng; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-m33"; 32 reg = <0>; 33 cpu-power-states = <&stop>; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 mpu: mpu@e000ed90 { 38 compatible = "arm,armv8m-mpu"; 39 reg = <0xe000ed90 0x40>; 40 }; 41 }; 42 }; 43 44 clocks { 45 clk_hse: clk-hse { 46 #clock-cells = <0>; 47 compatible = "st,stm32-hse-clock"; 48 status = "disabled"; 49 }; 50 51 clk_hsi: clk-hsi { 52 #clock-cells = <0>; 53 compatible = "st,stm32h7-hsi-clock"; 54 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */ 55 clock-frequency = <DT_FREQ_M(64)>; 56 status = "disabled"; 57 }; 58 59 clk_hsi48: clk-hsi48 { 60 #clock-cells = <0>; 61 compatible = "fixed-clock"; 62 clock-frequency = <DT_FREQ_M(48)>; 63 status = "disabled"; 64 }; 65 66 clk_csi: clk-csi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <DT_FREQ_M(4)>; 70 status = "disabled"; 71 }; 72 73 clk_lse: clk-lse { 74 #clock-cells = <0>; 75 compatible = "st,stm32-lse-clock"; 76 clock-frequency = <32768>; 77 driving-capability = <2>; 78 status = "disabled"; 79 }; 80 81 clk_lsi: clk-lsi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <DT_FREQ_K(32)>; 85 status = "disabled"; 86 }; 87 /* The pll scheme is similar to stm32u5 */ 88 pll1: pll: pll { 89 #clock-cells = <0>; 90 compatible = "st,stm32u5-pll-clock"; 91 status = "disabled"; 92 }; 93 94 pll2: pll2 { 95 #clock-cells = <0>; 96 compatible = "st,stm32u5-pll-clock"; 97 status = "disabled"; 98 }; 99 }; 100 101 mcos { 102 mco1: mco1 { 103 compatible = "st,stm32-clock-mco"; 104 status = "disabled"; 105 }; 106 107 mco2: mco2 { 108 compatible = "st,stm32-clock-mco"; 109 status = "disabled"; 110 }; 111 }; 112 113 soc { 114 flash: flash-controller@40022000 { 115 compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller"; 116 reg = <0x40022000 0x400>; 117 interrupts = <6 0>; 118 119 #address-cells = <1>; 120 #size-cells = <1>; 121 122 flash0: flash@8000000 { 123 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 124 125 write-block-size = <16>; 126 erase-block-size = <8192>; 127 /* maximum erase time(ms) for a 8K sector */ 128 max-erase-time = <5>; 129 }; 130 }; 131 132 backup_sram: memory@40036400 { 133 compatible = "zephyr,memory-region", "st,stm32-backup-sram"; 134 reg = <0x40036400 DT_SIZE_K(2)>; 135 clocks = <&rcc STM32_CLOCK(AHB1, 28U)>; 136 zephyr,memory-region = "BACKUP_SRAM"; 137 status = "disabled"; 138 }; 139 140 power-states { 141 stop: state0 { 142 compatible = "zephyr,power-state"; 143 power-state-name = "suspend-to-idle"; 144 substate-id = <1>; 145 min-residency-us = <20>; 146 }; 147 }; 148 149 rcc: rcc@44020c00 { 150 compatible = "st,stm32u5-rcc"; 151 clocks-controller; 152 #clock-cells = <2>; 153 reg = <0x44020c00 0x400>; 154 155 rctl: reset-controller { 156 compatible = "st,stm32-rcc-rctl"; 157 #reset-cells = <1>; 158 }; 159 }; 160 161 exti: interrupt-controller@44022000 { 162 compatible = "st,stm32g0-exti", "st,stm32-exti"; 163 interrupt-controller; 164 #interrupt-cells = <1>; 165 #address-cells = <1>; 166 reg = <0x44022000 0x400>; 167 num-lines = <16>; 168 interrupts = <11 0>, <12 0>, <13 0>, <14 0>, 169 <15 0>, <16 0>, <17 0>, <18 0>, 170 <19 0>, <20 0>, <21 0>, <22 0>, 171 <23 0>, <24 0>, <25 0>, <26 0>; 172 interrupt-names = "line0", "line1", "line2", "line3", 173 "line4", "line5", "line6", "line7", 174 "line8", "line9", "line10", "line11", 175 "line12", "line13", "line14", "line15"; 176 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 177 <4 1>, <5 1>, <6 1>, <7 1>, 178 <8 1>, <9 1>, <10 1>, <11 1>, 179 <12 1>, <13 1>, <14 1>, <15 1>; 180 }; 181 182 pinctrl: pin-controller@42020000 { 183 compatible = "st,stm32-pinctrl"; 184 #address-cells = <1>; 185 #size-cells = <1>; 186 reg = <0x42020000 0x2000>; 187 188 gpioa: gpio@42020000 { 189 compatible = "st,stm32-gpio"; 190 gpio-controller; 191 #gpio-cells = <2>; 192 reg = <0x42020000 0x400>; 193 clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; 194 }; 195 196 gpiob: gpio@42020400 { 197 compatible = "st,stm32-gpio"; 198 gpio-controller; 199 #gpio-cells = <2>; 200 reg = <0x42020400 0x400>; 201 clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; 202 }; 203 204 gpioc: gpio@42020800 { 205 compatible = "st,stm32-gpio"; 206 gpio-controller; 207 #gpio-cells = <2>; 208 reg = <0x42020800 0x400>; 209 clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; 210 }; 211 212 gpiod: gpio@42020c00 { 213 compatible = "st,stm32-gpio"; 214 gpio-controller; 215 #gpio-cells = <2>; 216 reg = <0x42020c00 0x400>; 217 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>; 218 }; 219 220 gpioh: gpio@42021c00 { 221 compatible = "st,stm32-gpio"; 222 gpio-controller; 223 #gpio-cells = <2>; 224 reg = <0x42021c00 0x400>; 225 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; 226 }; 227 }; 228 229 lptim1: timers@44004400 { 230 compatible = "st,stm32-lptim"; 231 clocks = <&rcc STM32_CLOCK(APB3, 11U)>; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 reg = <0x44004400 0x400>; 235 interrupts = <64 1>; 236 interrupt-names = "wakeup"; 237 status = "disabled"; 238 }; 239 240 lptim2: timers@40009400 { 241 compatible = "st,stm32-lptim"; 242 clocks = <&rcc STM32_CLOCK(APB1_2, 5U)>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 reg = <0x40009400 0x400>; 246 interrupts = <70 1>; 247 interrupt-names = "wakeup"; 248 status = "disabled"; 249 }; 250 251 usart1: serial@40013800 { 252 compatible = "st,stm32-usart", "st,stm32-uart"; 253 reg = <0x40013800 0x400>; 254 clocks = <&rcc STM32_CLOCK(APB2, 14U)>; 255 resets = <&rctl STM32_RESET(APB2, 14U)>; 256 interrupts = <58 0>; 257 status = "disabled"; 258 }; 259 260 usart2: serial@40004400 { 261 compatible = "st,stm32-usart", "st,stm32-uart"; 262 reg = <0x40004400 0x400>; 263 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 264 resets = <&rctl STM32_RESET(APB1L, 17U)>; 265 interrupts = <59 0>; 266 status = "disabled"; 267 }; 268 269 usart3: serial@40004800 { 270 compatible = "st,stm32-usart", "st,stm32-uart"; 271 reg = <0x40004800 0x400>; 272 clocks = <&rcc STM32_CLOCK(APB1, 18U)>; 273 resets = <&rctl STM32_RESET(APB1L, 18U)>; 274 interrupts = <60 0>; 275 status = "disabled"; 276 }; 277 278 lpuart1: serial@44002400 { 279 compatible = "st,stm32-lpuart", "st,stm32-uart"; 280 reg = <0x44002400 0x400>; 281 clocks = <&rcc STM32_CLOCK(APB3, 6U)>; 282 resets = <&rctl STM32_RESET(APB3, 6U)>; 283 interrupts = <63 0>; 284 status = "disabled"; 285 }; 286 287 iwdg: watchdog@40003000 { 288 compatible = "st,stm32-watchdog"; 289 reg = <0x40003000 0x400>; 290 status = "disabled"; 291 }; 292 293 wwdg: watchdog@40002c00 { 294 compatible = "st,stm32-window-watchdog"; 295 reg = <0x40002c00 0x400>; 296 clocks = <&rcc STM32_CLOCK(APB1, 11U)>; 297 interrupts = <0 7>; 298 status = "disabled"; 299 }; 300 301 dac1: dac@42028400 { 302 compatible = "st,stm32-dac"; 303 reg = <0x42028400 0x400>; 304 clocks = <&rcc STM32_CLOCK(AHB2, 11U)>; 305 status = "disabled"; 306 #io-channel-cells = <1>; 307 }; 308 309 adc1: adc@42028000 { 310 compatible = "st,stm32-adc"; 311 reg = <0x42028000 0x400>; 312 clocks = <&rcc STM32_CLOCK(AHB2, 10U)>; 313 interrupts = <37 0>; 314 status = "disabled"; 315 vref-mv = <3300>; 316 #io-channel-cells = <1>; 317 resolutions = <STM32_ADC_RES(12, 0x00) 318 STM32_ADC_RES(10, 0x01) 319 STM32_ADC_RES(8, 0x02) 320 STM32_ADC_RES(6, 0x03)>; 321 sampling-times = <3 7 13 25 48 93 248 641>; 322 st,adc-sequencer = "FULLY_CONFIGURABLE"; 323 st,adc-oversampler = "OVERSAMPLER_MINIMAL"; 324 }; 325 326 rtc: rtc@44007800 { 327 compatible = "st,stm32-rtc"; 328 reg = <0x44007800 0x400>; 329 interrupts = <2 0>; 330 clocks = <&rcc STM32_CLOCK(APB3, 21U)>; 331 prescaler = <32768>; 332 alarms-count = <2>; 333 alrm-exti-line = <17>; 334 status = "disabled"; 335 }; 336 337 timers1: timers@40012c00 { 338 compatible = "st,stm32-timers"; 339 reg = <0x40012c00 0x400>; 340 clocks = <&rcc STM32_CLOCK(APB2, 11U)>; 341 resets = <&rctl STM32_RESET(APB2, 11U)>; 342 interrupts = <41 0>, <42 0>, <43 0>, <44 0>; 343 interrupt-names = "brk", "up", "trgcom", "cc"; 344 status = "disabled"; 345 346 pwm { 347 compatible = "st,stm32-pwm"; 348 status = "disabled"; 349 #pwm-cells = <3>; 350 }; 351 }; 352 353 timers2: timers@40000000 { 354 compatible = "st,stm32-timers"; 355 reg = <0x40000000 0x400>; 356 clocks = <&rcc STM32_CLOCK(APB1, 0U)>; 357 resets = <&rctl STM32_RESET(APB1L, 0U)>; 358 interrupts = <45 0>; 359 interrupt-names = "global"; 360 status = "disabled"; 361 362 pwm { 363 compatible = "st,stm32-pwm"; 364 status = "disabled"; 365 #pwm-cells = <3>; 366 }; 367 368 counter { 369 compatible = "st,stm32-counter"; 370 status = "disabled"; 371 }; 372 }; 373 374 timers3: timers@40000400 { 375 compatible = "st,stm32-timers"; 376 reg = <0x40000400 0x400>; 377 clocks = <&rcc STM32_CLOCK(APB1, 1U)>; 378 resets = <&rctl STM32_RESET(APB1L, 1U)>; 379 interrupts = <46 0>; 380 interrupt-names = "global"; 381 status = "disabled"; 382 383 pwm { 384 compatible = "st,stm32-pwm"; 385 status = "disabled"; 386 #pwm-cells = <3>; 387 }; 388 389 counter { 390 compatible = "st,stm32-counter"; 391 status = "disabled"; 392 }; 393 }; 394 395 timers6: timers@40001000 { 396 compatible = "st,stm32-timers"; 397 reg = <0x40001000 0x400>; 398 clocks = <&rcc STM32_CLOCK(APB1, 4U)>; 399 resets = <&rctl STM32_RESET(APB1L, 4U)>; 400 interrupts = <49 0>; 401 interrupt-names = "global"; 402 status = "disabled"; 403 404 pwm { 405 compatible = "st,stm32-pwm"; 406 status = "disabled"; 407 #pwm-cells = <3>; 408 }; 409 410 counter { 411 compatible = "st,stm32-counter"; 412 status = "disabled"; 413 }; 414 }; 415 416 timers7: timers@40001400 { 417 compatible = "st,stm32-timers"; 418 reg = <0x40001400 0x400>; 419 clocks = <&rcc STM32_CLOCK(APB1, 5U)>; 420 resets = <&rctl STM32_RESET(APB1L, 5U)>; 421 interrupts = <50 0>; 422 interrupt-names = "global"; 423 status = "disabled"; 424 425 pwm { 426 compatible = "st,stm32-pwm"; 427 status = "disabled"; 428 #pwm-cells = <3>; 429 }; 430 431 counter { 432 compatible = "st,stm32-counter"; 433 status = "disabled"; 434 }; 435 }; 436 437 i2c1: i2c@40005400 { 438 compatible = "st,stm32-i2c-v2"; 439 clock-frequency = <I2C_BITRATE_STANDARD>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 reg = <0x40005400 0x400>; 443 clocks = <&rcc STM32_CLOCK(APB1, 21U)>; 444 interrupts = <51 0>, <52 0>; 445 interrupt-names = "event", "error"; 446 status = "disabled"; 447 }; 448 449 i2c2: i2c@40005800 { 450 compatible = "st,stm32-i2c-v2"; 451 clock-frequency = <I2C_BITRATE_STANDARD>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 reg = <0x40005800 0x400>; 455 clocks = <&rcc STM32_CLOCK(APB1, 22U)>; 456 interrupts = <53 0>, <54 0>; 457 interrupt-names = "event", "error"; 458 status = "disabled"; 459 }; 460 461 i3c1: i3c@40005c00 { 462 compatible = "st,stm32-i3c"; 463 reg = <0x40005c00 0x400>; 464 interrupts = <123 0>, <124 0>; 465 interrupt-names = "event", "error"; 466 #address-cells = <3>; 467 #size-cells = <0>; 468 clocks = <&rcc STM32_CLOCK(APB1, 23U)>; 469 resets = <&rctl STM32_RESET(APB1L, 23U)>; 470 zephyr,pm-device-runtime-auto; 471 status = "disabled"; 472 }; 473 474 i3c2: i3c@44003000 { 475 compatible = "st,stm32-i3c"; 476 reg = <0x44003000 0x400>; 477 interrupts = <131 0>, <132 0>; 478 interrupt-names = "event", "error"; 479 #address-cells = <3>; 480 #size-cells = <0>; 481 clocks = <&rcc STM32_CLOCK(APB3, 9U)>; 482 resets = <&rctl STM32_RESET(APB3, 9U)>; 483 zephyr,pm-device-runtime-auto; 484 status = "disabled"; 485 }; 486 487 spi1: spi@40013000 { 488 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 reg = <0x40013000 0x400>; 492 interrupts = <55 5>; 493 clocks = <&rcc STM32_CLOCK(APB2, 12U)>, 494 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; 495 status = "disabled"; 496 }; 497 498 spi2: spi@40003800 { 499 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 reg = <0x40003800 0x400>; 503 interrupts = <56 5>; 504 clocks = <&rcc STM32_CLOCK(APB1, 14U)>, 505 <&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>; 506 status = "disabled"; 507 }; 508 509 spi3: spi@40003c00 { 510 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 reg = <0x40003c00 0x400>; 514 interrupts = <57 5>; 515 clocks = <&rcc STM32_CLOCK(APB1, 15U)>, 516 <&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>; 517 status = "disabled"; 518 }; 519 520 fdcan1: can@4000a400 { 521 compatible = "st,stm32-fdcan"; 522 reg = <0x4000a400 0x400>, <0x4000ac00 0x350>; 523 reg-names = "m_can", "message_ram"; 524 interrupts = <39 0>, <40 0>; 525 interrupt-names = "int0", "int1"; 526 clocks = <&rcc STM32_CLOCK(APB1_2, 9U)>; 527 bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; 528 status = "disabled"; 529 }; 530 531 rng: rng@420c0800 { 532 compatible = "st,stm32-rng"; 533 reg = <0x420c0800 0x400>; 534 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>; 535 interrupts = <114 0>; 536 nist-config = <0xf00d00>; 537 health-test-config = <0xaac7>; 538 status = "disabled"; 539 }; 540 541 mac: ethernet@40028000 { 542 compatible = "st,stm32h7-ethernet", "st,stm32-ethernet"; 543 reg = <0x40028000 0x8000>; 544 interrupts = <106 0>; 545 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; 546 clocks = <&rcc STM32_CLOCK(AHB1, 19U)>, 547 <&rcc STM32_CLOCK(AHB1, 20U)>, 548 <&rcc STM32_CLOCK(AHB1, 21U)>; 549 status = "disabled"; 550 551 mdio: mdio { 552 compatible = "st,stm32-mdio"; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 status = "disabled"; 556 }; 557 }; 558 559 gpdma1: dma@40020000 { 560 compatible = "st,stm32u5-dma"; 561 #dma-cells = <3>; 562 reg = <0x40020000 0x1000>; 563 interrupts = <27 0 28 0 29 0 30 0 31 0 32 0 33 0 34 0>; 564 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; 565 dma-channels = <8>; 566 dma-requests = <140>; 567 dma-offset = <0>; 568 status = "disabled"; 569 }; 570 571 gpdma2: dma@40021000 { 572 compatible = "st,stm32u5-dma"; 573 #dma-cells = <3>; 574 reg = <0x40021000 0x1000>; 575 interrupts = <90 0 91 0 92 0 93 0 94 0 95 0 96 0 97 0>; 576 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; 577 dma-channels = <8>; 578 dma-requests = <140>; 579 dma-offset = <8>; 580 status = "disabled"; 581 }; 582 583 i2s1: i2s@40013000 { 584 compatible = "st,stm32h7-i2s", "st,stm32-i2s"; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 reg = <0x40013000 0x400>; 588 clocks = <&rcc STM32_CLOCK(APB2, 12U)>, 589 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; 590 dmas = <&gpdma1 0 7 (STM32_DMA_PERIPH_TX |STM32_DMA_16BITS | \ 591 STM32_DMA_PRIORITY_HIGH) 592 &gpdma1 1 6 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | \ 593 STM32_DMA_PRIORITY_HIGH)>; 594 dma-names = "tx", "rx"; 595 interrupts = <55 3>; 596 status = "disabled"; 597 }; 598 599 i2s2: i2s@40003800 { 600 compatible = "st,stm32h7-i2s", "st,stm32-i2s"; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 reg = <0x40003800 0x400>; 604 clocks = <&rcc STM32_CLOCK(APB1, 14U)>, 605 <&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>; 606 dmas = <&gpdma1 2 9 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | \ 607 STM32_DMA_PRIORITY_HIGH) 608 &gpdma1 3 8 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | \ 609 STM32_DMA_PRIORITY_HIGH)>; 610 dma-names = "tx", "rx"; 611 interrupts = <56 3>; 612 status = "disabled"; 613 }; 614 615 i2s3: i2s@40003c00 { 616 compatible = "st,stm32h7-i2s", "st,stm32-i2s"; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 reg = <0x40003c00 0x400>; 620 clocks = <&rcc STM32_CLOCK(APB1, 15U)>, 621 <&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>; 622 dmas = <&gpdma1 4 11 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | \ 623 STM32_DMA_PRIORITY_HIGH) 624 &gpdma1 5 10 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | \ 625 STM32_DMA_PRIORITY_HIGH)>; 626 dma-names = "tx", "rx"; 627 interrupts = <57 3>; 628 status = "disabled"; 629 }; 630 631 usb: usb@40016000 { 632 compatible = "st,stm32-usb"; 633 reg = <0x40016000 0x400>; 634 interrupts = <74 0>; 635 interrupt-names = "usb"; 636 num-bidir-endpoints = <8>; 637 ram-size = <2048>; 638 phys = <&usb_fs_phy>; 639 clocks = <&rcc STM32_CLOCK(APB2, 24U)>, 640 <&rcc STM32_SRC_HSI48 USB_SEL(3)>; 641 status = "disabled"; 642 }; 643 644 digi_die_temp: digi_dietemp@40008c00 { 645 compatible = "st,stm32-digi-temp"; 646 reg = <0x40008c00 0x400>; 647 interrupts = <113 0>; 648 interrupt-names = "digi_temp"; 649 clocks = <&rcc STM32_CLOCK(APB1_2, 3U)>; 650 status = "disabled"; 651 }; 652 }; 653 654 die_temp: dietemp { 655 compatible = "st,stm32-temp-cal"; 656 ts-cal1-addr = <0x08fff814>; 657 ts-cal2-addr = <0x08fff818>; 658 ts-cal1-temp = <30>; 659 ts-cal2-temp = <130>; 660 ts-cal-vrefanalog = <3300>; 661 ts-cal-resolution = <12>; 662 io-channels = <&adc1 16>; 663 status = "disabled"; 664 }; 665 666 vref: vref { 667 compatible = "st,stm32-vref"; 668 vrefint-cal-addr = <0x08FFF810>; 669 vrefint-cal-mv = <3300>; 670 io-channels = <&adc1 17>; 671 status = "disabled"; 672 }; 673 674 vbat: vbat { 675 compatible = "st,stm32-vbat"; 676 ratio = <4>; 677 io-channels = <&adc1 2>; 678 status = "disabled"; 679 }; 680 681 usb_fs_phy: usbphy { 682 compatible = "usb-nop-xceiv"; 683 #phy-cells = <0>; 684 }; 685 686 smbus1: smbus1 { 687 compatible = "st,stm32-smbus"; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 i2c = <&i2c1>; 691 status = "disabled"; 692 }; 693 694 smbus2: smbus2 { 695 compatible = "st,stm32-smbus"; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 i2c = <&i2c2>; 699 status = "disabled"; 700 }; 701}; 702 703&nvic { 704 arm,num-irq-priority-bits = <4>; 705}; 706
