/*
 * Copyright (c) 2023-2024 STMicroelectronics
 *
 * SPDX-License-Identifier: Apache-2.0
 */


#include <arm/armv8-m.dtsi>
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/clock/stm32h5_clock.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/reset/stm32h5_reset.h>
#include <zephyr/dt-bindings/dma/stm32_dma.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
#include <freq.h>

/ {
	chosen {
		zephyr,flash-controller = &flash;
		zephyr,entropy = &rng;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m33";
			reg = <0>;
			cpu-power-states = <&stop>;
			#address-cells = <1>;
			#size-cells = <1>;

			mpu: mpu@e000ed90 {
				compatible = "arm,armv8m-mpu";
				reg = <0xe000ed90 0x40>;
			};
		};
	};

	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "st,stm32-hse-clock";
			status = "disabled";
		};

		clk_hsi: clk-hsi {
			#clock-cells = <0>;
			compatible = "st,stm32h7-hsi-clock";
			hsi-div = <1>;		/* HSI RC: 64MHz, hsi_clk = 64MHz */
			clock-frequency = <DT_FREQ_M(64)>;
			status = "disabled";
		};

		clk_hsi48: clk-hsi48 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_M(48)>;
			status = "disabled";
		};

		clk_csi: clk-csi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_M(4)>;
			status = "disabled";
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "st,stm32-lse-clock";
			clock-frequency = <32768>;
			driving-capability = <2>;
			status = "disabled";
		};

		clk_lsi: clk-lsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_K(32)>;
			status = "disabled";
		};
		/* The pll scheme is similar to stm32u5 */
		pll1: pll: pll {
			#clock-cells = <0>;
			compatible = "st,stm32u5-pll-clock";
			status = "disabled";
		};

		pll2: pll2 {
			#clock-cells = <0>;
			compatible = "st,stm32u5-pll-clock";
			status = "disabled";
		};
	};

	mcos {
		mco1: mco1 {
			compatible = "st,stm32-clock-mco";
			status = "disabled";
		};

		mco2: mco2 {
			compatible = "st,stm32-clock-mco";
			status = "disabled";
		};
	};

	soc {
		flash: flash-controller@40022000 {
			compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller";
			reg = <0x40022000 0x400>;
			interrupts = <6 0>;

			#address-cells = <1>;
			#size-cells = <1>;

			flash0: flash@8000000 {
				compatible = "st,stm32-nv-flash", "soc-nv-flash";

				write-block-size = <16>;
				erase-block-size = <8192>;
				/* maximum erase time(ms) for a 8K sector */
				max-erase-time = <5>;
			};
		};

		backup_sram: memory@40036400 {
			compatible = "zephyr,memory-region", "st,stm32-backup-sram";
			reg = <0x40036400 DT_SIZE_K(2)>;
			clocks = <&rcc STM32_CLOCK(AHB1, 28U)>;
			zephyr,memory-region = "BACKUP_SRAM";
			status = "disabled";
		};

		power-states {
			stop: state0 {
				compatible = "zephyr,power-state";
				power-state-name = "suspend-to-idle";
				substate-id = <1>;
				min-residency-us = <20>;
			};
		};

		rcc: rcc@44020c00 {
			compatible = "st,stm32u5-rcc";
			clocks-controller;
			#clock-cells = <2>;
			reg = <0x44020c00 0x400>;

			rctl: reset-controller {
				compatible = "st,stm32-rcc-rctl";
				#reset-cells = <1>;
			};
		};

		exti: interrupt-controller@44022000 {
			compatible = "st,stm32g0-exti", "st,stm32-exti";
			interrupt-controller;
			#interrupt-cells = <1>;
			#address-cells = <1>;
			reg = <0x44022000 0x400>;
			num-lines = <16>;
			interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
				     <15 0>, <16 0>, <17 0>, <18 0>,
				     <19 0>, <20 0>, <21 0>, <22 0>,
				     <23 0>, <24 0>, <25 0>, <26 0>;
			interrupt-names = "line0", "line1", "line2", "line3",
					  "line4", "line5", "line6", "line7",
					  "line8", "line9", "line10", "line11",
					  "line12", "line13", "line14", "line15";
			line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
				      <4 1>, <5 1>, <6 1>, <7 1>,
				      <8 1>, <9 1>, <10 1>, <11 1>,
				      <12 1>, <13 1>, <14 1>, <15 1>;
		};

		pinctrl: pin-controller@42020000 {
			compatible = "st,stm32-pinctrl";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x42020000 0x2000>;

			gpioa: gpio@42020000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x42020000 0x400>;
				clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
			};

			gpiob: gpio@42020400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x42020400 0x400>;
				clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
			};

			gpioc: gpio@42020800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x42020800 0x400>;
				clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
			};

			gpiod: gpio@42020c00 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x42020c00 0x400>;
				clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
			};

			gpioh: gpio@42021c00 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x42021c00 0x400>;
				clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
			};
		};

		lptim1: timers@44004400 {
			compatible = "st,stm32-lptim";
			clocks = <&rcc STM32_CLOCK(APB3, 11U)>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x44004400 0x400>;
			interrupts = <64 1>;
			interrupt-names = "wakeup";
			status = "disabled";
		};

		lptim2: timers@40009400 {
			compatible = "st,stm32-lptim";
			clocks = <&rcc STM32_CLOCK(APB1_2, 5U)>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40009400 0x400>;
			interrupts = <70 1>;
			interrupt-names = "wakeup";
			status = "disabled";
		};

		usart1: serial@40013800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40013800 0x400>;
			clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
			resets = <&rctl STM32_RESET(APB2, 14U)>;
			interrupts = <58 0>;
			status = "disabled";
		};

		usart2: serial@40004400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
			resets = <&rctl STM32_RESET(APB1L, 17U)>;
			interrupts = <59 0>;
			status = "disabled";
		};

		usart3: serial@40004800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004800 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
			resets = <&rctl STM32_RESET(APB1L, 18U)>;
			interrupts = <60 0>;
			status = "disabled";
		};

		lpuart1: serial@44002400 {
			compatible = "st,stm32-lpuart", "st,stm32-uart";
			reg = <0x44002400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB3, 6U)>;
			resets = <&rctl STM32_RESET(APB3, 6U)>;
			interrupts = <63 0>;
			status = "disabled";
		};

		iwdg: watchdog@40003000 {
			compatible = "st,stm32-watchdog";
			reg = <0x40003000 0x400>;
			status = "disabled";
		};

		wwdg: watchdog@40002c00 {
			compatible = "st,stm32-window-watchdog";
			reg = <0x40002c00 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
			interrupts = <0 7>;
			status = "disabled";
		};

		dac1: dac@42028400 {
			compatible = "st,stm32-dac";
			reg = <0x42028400 0x400>;
			clocks = <&rcc STM32_CLOCK(AHB2, 11U)>;
			status = "disabled";
			#io-channel-cells = <1>;
		};

		adc1: adc@42028000 {
			compatible = "st,stm32-adc";
			reg = <0x42028000 0x400>;
			clocks = <&rcc STM32_CLOCK(AHB2, 10U)>;
			interrupts = <37 0>;
			status = "disabled";
			vref-mv = <3300>;
			#io-channel-cells = <1>;
			resolutions = <STM32_ADC_RES(12, 0x00)
				       STM32_ADC_RES(10, 0x01)
				       STM32_ADC_RES(8, 0x02)
				       STM32_ADC_RES(6, 0x03)>;
			sampling-times = <3 7 13 25 48 93 248 641>;
			st,adc-sequencer = "FULLY_CONFIGURABLE";
			st,adc-oversampler = "OVERSAMPLER_MINIMAL";
		};

		rtc: rtc@44007800 {
			compatible = "st,stm32-rtc";
			reg = <0x44007800 0x400>;
			interrupts = <2 0>;
			clocks = <&rcc STM32_CLOCK(APB3, 21U)>;
			prescaler = <32768>;
			alarms-count = <2>;
			alrm-exti-line = <17>;
			status = "disabled";
		};

		timers1: timers@40012c00 {
			compatible = "st,stm32-timers";
			reg = <0x40012c00 0x400>;
			clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
			resets = <&rctl STM32_RESET(APB2, 11U)>;
			interrupts = <41 0>, <42 0>, <43 0>, <44 0>;
			interrupt-names = "brk", "up", "trgcom", "cc";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timers2: timers@40000000 {
			compatible = "st,stm32-timers";
			reg = <0x40000000 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
			resets = <&rctl STM32_RESET(APB1L, 0U)>;
			interrupts = <45 0>;
			interrupt-names = "global";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers3: timers@40000400 {
			compatible = "st,stm32-timers";
			reg = <0x40000400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
			resets = <&rctl STM32_RESET(APB1L, 1U)>;
			interrupts = <46 0>;
			interrupt-names = "global";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers6: timers@40001000 {
			compatible = "st,stm32-timers";
			reg = <0x40001000 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
			resets = <&rctl STM32_RESET(APB1L, 4U)>;
			interrupts = <49 0>;
			interrupt-names = "global";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers7: timers@40001400 {
			compatible = "st,stm32-timers";
			reg = <0x40001400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
			resets = <&rctl STM32_RESET(APB1L, 5U)>;
			interrupts = <50 0>;
			interrupt-names = "global";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		i2c1: i2c@40005400 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40005400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
			interrupts = <51 0>, <52 0>;
			interrupt-names = "event", "error";
			status = "disabled";
		};

		i2c2: i2c@40005800 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40005800 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
			interrupts = <53 0>, <54 0>;
			interrupt-names = "event", "error";
			status = "disabled";
		};

		i3c1: i3c@40005c00 {
			compatible = "st,stm32-i3c";
			reg = <0x40005c00 0x400>;
			interrupts = <123 0>, <124 0>;
			interrupt-names = "event", "error";
			#address-cells = <3>;
			#size-cells = <0>;
			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
			resets = <&rctl STM32_RESET(APB1L, 23U)>;
			zephyr,pm-device-runtime-auto;
			status = "disabled";
		};

		i3c2: i3c@44003000 {
			compatible = "st,stm32-i3c";
			reg = <0x44003000 0x400>;
			interrupts = <131 0>, <132 0>;
			interrupt-names = "event", "error";
			#address-cells = <3>;
			#size-cells = <0>;
			clocks = <&rcc STM32_CLOCK(APB3, 9U)>;
			resets = <&rctl STM32_RESET(APB3, 9U)>;
			zephyr,pm-device-runtime-auto;
			status = "disabled";
		};

		spi1: spi@40013000 {
			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40013000 0x400>;
			interrupts = <55 5>;
			clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
				 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
			status = "disabled";
		};

		spi2: spi@40003800 {
			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003800 0x400>;
			interrupts = <56 5>;
			clocks = <&rcc STM32_CLOCK(APB1, 14U)>,
				 <&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>;
			status = "disabled";
		};

		spi3: spi@40003c00 {
			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003c00 0x400>;
			interrupts = <57 5>;
			clocks = <&rcc STM32_CLOCK(APB1, 15U)>,
				 <&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>;
			status = "disabled";
		};

		fdcan1: can@4000a400 {
			compatible = "st,stm32-fdcan";
			reg = <0x4000a400 0x400>, <0x4000ac00 0x350>;
			reg-names = "m_can", "message_ram";
			interrupts = <39 0>, <40 0>;
			interrupt-names = "int0", "int1";
			clocks = <&rcc STM32_CLOCK(APB1_2, 9U)>;
			bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
			status = "disabled";
		};

		rng: rng@420c0800 {
			compatible = "st,stm32-rng";
			reg = <0x420c0800 0x400>;
			clocks = <&rcc STM32_CLOCK(AHB2, 18U)>;
			interrupts = <114 0>;
			nist-config = <0xf00d00>;
			health-test-config = <0xaac7>;
			status = "disabled";
		};

		mac: ethernet@40028000 {
			compatible = "st,stm32h7-ethernet", "st,stm32-ethernet";
			reg = <0x40028000 0x8000>;
			interrupts = <106 0>;
			clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
			clocks = <&rcc STM32_CLOCK(AHB1, 19U)>,
				 <&rcc STM32_CLOCK(AHB1, 20U)>,
				 <&rcc STM32_CLOCK(AHB1, 21U)>;
			status = "disabled";

			mdio: mdio {
				compatible = "st,stm32-mdio";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		gpdma1: dma@40020000 {
			compatible = "st,stm32u5-dma";
			#dma-cells = <3>;
			reg = <0x40020000 0x1000>;
			interrupts = <27 0 28 0 29 0 30 0 31 0 32 0 33 0 34 0>;
			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
			dma-channels = <8>;
			dma-requests = <140>;
			dma-offset = <0>;
			status = "disabled";
		};

		gpdma2: dma@40021000 {
			compatible = "st,stm32u5-dma";
			#dma-cells = <3>;
			reg = <0x40021000 0x1000>;
			interrupts = <90 0 91 0 92 0 93 0 94 0 95 0 96 0 97 0>;
			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
			dma-channels = <8>;
			dma-requests = <140>;
			dma-offset = <8>;
			status = "disabled";
		};

		i2s1: i2s@40013000 {
			compatible = "st,stm32h7-i2s", "st,stm32-i2s";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40013000 0x400>;
			clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
				<&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
			dmas = <&gpdma1 0 7 (STM32_DMA_PERIPH_TX |STM32_DMA_16BITS | \
					STM32_DMA_PRIORITY_HIGH)
				&gpdma1 1 6 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | \
					STM32_DMA_PRIORITY_HIGH)>;
			dma-names = "tx", "rx";
			interrupts = <55 3>;
			status = "disabled";
		};

		i2s2: i2s@40003800 {
			compatible = "st,stm32h7-i2s", "st,stm32-i2s";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003800 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 14U)>,
				<&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>;
			dmas = <&gpdma1 2 9 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | \
					STM32_DMA_PRIORITY_HIGH)
				&gpdma1 3 8 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | \
					STM32_DMA_PRIORITY_HIGH)>;
			dma-names = "tx", "rx";
			interrupts = <56 3>;
			status = "disabled";
		};

		i2s3: i2s@40003c00 {
			compatible = "st,stm32h7-i2s", "st,stm32-i2s";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003c00 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 15U)>,
				<&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>;
			dmas = <&gpdma1 4 11 (STM32_DMA_PERIPH_TX  | STM32_DMA_16BITS | \
					STM32_DMA_PRIORITY_HIGH)
				&gpdma1 5 10 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | \
					STM32_DMA_PRIORITY_HIGH)>;
			dma-names = "tx", "rx";
			interrupts = <57 3>;
			status = "disabled";
		};

		usb: usb@40016000 {
			compatible = "st,stm32-usb";
			reg = <0x40016000 0x400>;
			interrupts = <74 0>;
			interrupt-names = "usb";
			num-bidir-endpoints = <8>;
			ram-size = <2048>;
			phys = <&usb_fs_phy>;
			clocks = <&rcc STM32_CLOCK(APB2, 24U)>,
				 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
			status = "disabled";
		};

		digi_die_temp: digi_dietemp@40008c00 {
			compatible = "st,stm32-digi-temp";
			reg = <0x40008c00 0x400>;
			interrupts = <113 0>;
			interrupt-names = "digi_temp";
			clocks = <&rcc STM32_CLOCK(APB1_2, 3U)>;
			status = "disabled";
		};
	};

	die_temp: dietemp {
		compatible = "st,stm32-temp-cal";
		ts-cal1-addr = <0x08fff814>;
		ts-cal2-addr = <0x08fff818>;
		ts-cal1-temp = <30>;
		ts-cal2-temp = <130>;
		ts-cal-vrefanalog = <3300>;
		ts-cal-resolution = <12>;
		io-channels = <&adc1 16>;
		status = "disabled";
	};

	vref: vref {
		compatible = "st,stm32-vref";
		vrefint-cal-addr = <0x08FFF810>;
		vrefint-cal-mv = <3300>;
		io-channels = <&adc1 17>;
		status = "disabled";
	};

	vbat: vbat {
		compatible = "st,stm32-vbat";
		ratio = <4>;
		io-channels = <&adc1 2>;
		status = "disabled";
	};

	usb_fs_phy: usbphy {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};

	smbus1: smbus1 {
		compatible = "st,stm32-smbus";
		#address-cells = <1>;
		#size-cells = <0>;
		i2c = <&i2c1>;
		status = "disabled";
	};

	smbus2: smbus2 {
		compatible = "st,stm32-smbus";
		#address-cells = <1>;
		#size-cells = <0>;
		i2c = <&i2c2>;
		status = "disabled";
	};
};

&nvic {
	arm,num-irq-priority-bits = <4>;
};