1/*
2 * Copyright (c) 2020 Thomas Stranger
3 * Copyright (c) 2021 G-Technologies Sdn. Bhd.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <st/g0/stm32g071.dtsi>
9
10/ {
11
12	clocks {
13		clk_hsi48: clk-hsi48 {
14			#clock-cells = <0>;
15			compatible = "st,stm32-hsi48-clock";
16			clock-frequency = <DT_FREQ_M(48)>;
17			status = "disabled";
18		};
19	};
20
21	soc {
22		compatible = "st,stm32g0b1", "st,stm32g0", "simple-bus";
23
24
25		pinctrl: pin-controller@50000000 {
26			gpioe: gpio@50001000 {
27				compatible = "st,stm32-gpio";
28				gpio-controller;
29				#gpio-cells = <2>;
30				reg = <0x50001000 0x400>;
31				clocks = <&rcc STM32_CLOCK(IOP, 4U)>;
32			};
33		};
34
35		fdcan1: can@40006400 {
36			compatible = "st,stm32-fdcan";
37			reg = <0x40006400 0x400>, <0x4000b400 0x350>;
38			reg-names = "m_can", "message_ram";
39			interrupts = <21 0>, <22 0>;
40			interrupt-names = "int0", "int1";
41			clocks = <&rcc STM32_CLOCK(APB1, 12U)>;
42			bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
43			status = "disabled";
44		};
45
46		fdcan2: can@40006800 {
47			compatible = "st,stm32-fdcan";
48			reg = <0x40006800 0x400>, <0x4000b750 0x350>;
49			reg-names = "m_can", "message_ram";
50			interrupts = <21 0>, <22 0>;
51			interrupt-names = "int0", "int1";
52			clocks = <&rcc STM32_CLOCK(APB1, 12U)>;
53			bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
54			status = "disabled";
55		};
56
57		usart5: serial@40005000 {
58			compatible = "st,stm32-usart", "st,stm32-uart";
59			reg = <0x40005000 0x400>;
60			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
61			resets = <&rctl STM32_RESET(APB1L, 8U)>;
62			interrupts = <29 0>;
63			status = "disabled";
64		};
65
66		usart6: serial@40013c00 {
67			compatible = "st,stm32-usart", "st,stm32-uart";
68			reg = <0x40013c00 0x400>;
69			clocks = <&rcc STM32_CLOCK(APB1, 9U)>;
70			resets = <&rctl STM32_RESET(APB1L, 9U)>;
71			interrupts = <29 0>;
72			status = "disabled";
73		};
74
75		lpuart2: serial@40008400 {
76			compatible = "st,stm32-lpuart", "st,stm32-uart";
77			reg = <0x40008400 0x400>;
78			clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
79			resets = <&rctl STM32_RESET(APB1L, 7U)>;
80			interrupts = <28 0>;
81			status = "disabled";
82		};
83
84		timers4: timers@40000800 {
85			compatible = "st,stm32-timers";
86			reg = <0x40000800 0x400>;
87			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
88			resets = <&rctl STM32_RESET(APB1L, 2U)>;
89			interrupts = <16 0>;
90			interrupt-names = "global";
91			st,prescaler = <0>;
92			status = "disabled";
93
94			pwm {
95				compatible = "st,stm32-pwm";
96				status = "disabled";
97				#pwm-cells = <3>;
98			};
99		};
100
101		i2c3: i2c@40008800 {
102			compatible = "st,stm32-i2c-v2";
103			clock-frequency = <I2C_BITRATE_STANDARD>;
104			#address-cells = <1>;
105			#size-cells = <0>;
106			reg = <0x40008800 0x400>;
107			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
108			interrupts = <24 0>;
109			interrupt-names = "combined";
110			status = "disabled";
111		};
112
113		spi3: spi@40003c00 {
114			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
115			#address-cells = <1>;
116			#size-cells = <0>;
117			reg = <0x40003c00 0x400>;
118			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
119			interrupts = <26 3>;
120			status = "disabled";
121		};
122
123		dma2: dma@40020400 {
124			compatible = "st,stm32-dma-v2";
125			#dma-cells = <3>;
126			reg = <0x40020400 0x400>;
127			interrupts = <11 0 11 0 11 0 11 0 11 0>;
128			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
129			dma-requests = <5>;
130			dma-offset = <7>;
131			status = "disabled";
132		};
133
134		dmamux1: dmamux@40020800 {
135			dma-channels = <12>;
136			dma-requests = <73>;
137		};
138
139		usb: usb@40005c00 {
140			compatible = "st,stm32-usb";
141			reg = <0x40005c00 0x400>;
142			interrupts = <8 0>;
143			interrupt-names = "usb";
144			num-bidir-endpoints = <8>;
145			ram-size = <2048>;
146			phys = <&usb_fs_phy>;
147			clocks = <&rcc STM32_CLOCK(APB1, 13U)>,
148				 <&rcc STM32_SRC_HSI48 USB_SEL(0)>;
149			status = "disabled";
150		};
151	};
152
153	usb_fs_phy: usbphy {
154		compatible = "usb-nop-xceiv";
155		#phy-cells = <0>;
156	};
157
158	smbus3: smbus3 {
159		compatible = "st,stm32-smbus";
160		#address-cells = <1>;
161		#size-cells = <0>;
162		i2c = <&i2c3>;
163		status = "disabled";
164	};
165};
166