Lines Matching +full:stm32 +full:- +full:dma +full:- +full:v2
5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/clock/stm32l0_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/adc/adc.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32l0_reset.h>
22 zephyr,flash-controller = &flash;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 compatible = "arm,cortex-m0+";
33 cpu-power-states = <&stop>;
36 power-states {
38 compatible = "zephyr,power-state";
39 power-state-name = "suspend-to-idle";
40 min-residency-us = <2000>;
41 exit-latency-us = <750>;
47 compatible = "mmio-sram";
51 clk_hse: clk-hse {
52 #clock-cells = <0>;
53 compatible = "st,stm32-hse-clock";
57 clk_hsi: clk-hsi {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <DT_FREQ_M(16)>;
64 clk_msi: clk-msi {
65 #clock-cells = <0>;
66 compatible = "st,stm32l0-msi-clock";
67 msi-range = <5>; /* 2.1MHz (reset value) */
71 clk_lse: clk-lse {
72 #clock-cells = <0>;
73 compatible = "st,stm32-lse-clock";
74 clock-frequency = <32768>;
75 driving-capability = <0>;
79 clk_lsi: clk-lsi {
80 #clock-cells = <0>;
81 compatible = "fixed-clock";
82 clock-frequency = <DT_FREQ_K(37)>;
87 #clock-cells = <0>;
88 compatible = "st,stm32l0-pll-clock";
95 compatible = "st,stm32-rtc";
100 alarms-count = <2>;
101 alrm-exti-line = <17>;
105 compatible = "st,stm32-bbram";
106 st,backup-regs = <5>;
111 flash: flash-controller@40022000 {
112 compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
116 #address-cells = <1>;
117 #size-cells = <1>;
120 compatible = "st,stm32l0-nv-flash", "st,stm32-nv-flash",
121 "soc-nv-flash";
123 write-block-size = <4>;
125 max-erase-time = <4>;
130 compatible = "st,stm32-rcc";
131 #clock-cells = <2>;
134 rctl: reset-controller {
135 compatible = "st,stm32-rcc-rctl";
136 #reset-cells = <1>;
140 exti: interrupt-controller@40010400 {
141 compatible = "st,stm32-exti";
142 interrupt-controller;
143 #interrupt-cells = <1>;
144 #address-cells = <1>;
146 num-lines = <16>;
148 interrupt-names = "line0-1", "line2-3", "line4-15";
149 line-ranges = <0 2>, <2 2>, <4 12>;
152 pinctrl: pin-controller@50000000 {
153 compatible = "st,stm32-pinctrl";
154 #address-cells = <1>;
155 #size-cells = <1>;
159 compatible = "st,stm32-gpio";
160 gpio-controller;
161 #gpio-cells = <2>;
167 compatible = "st,stm32-gpio";
168 gpio-controller;
169 #gpio-cells = <2>;
175 compatible = "st,stm32-gpio";
176 gpio-controller;
177 #gpio-cells = <2>;
183 compatible = "st,stm32-gpio";
184 gpio-controller;
185 #gpio-cells = <2>;
191 compatible = "st,stm32-gpio";
192 gpio-controller;
193 #gpio-cells = <2>;
200 compatible = "st,stm32-watchdog";
206 compatible = "st,stm32-window-watchdog";
214 compatible = "st,stm32-usart", "st,stm32-uart";
223 compatible = "st,stm32-lpuart", "st,stm32-uart";
232 compatible = "st,stm32-i2c-v2";
233 clock-frequency = <I2C_BITRATE_STANDARD>;
234 #address-cells = <1>;
235 #size-cells = <0>;
239 interrupt-names = "combined";
244 compatible = "st,stm32-spi";
245 #address-cells = <1>;
246 #size-cells = <0>;
254 compatible = "st,stm32-timers";
259 interrupt-names = "global";
264 compatible = "st,stm32-pwm";
266 #pwm-cells = <3>;
270 compatible = "st,stm32-counter";
276 compatible = "st,stm32-timers";
281 interrupt-names = "global";
286 compatible = "st,stm32-pwm";
288 #pwm-cells = <3>;
292 compatible = "st,stm32-counter";
298 compatible = "st,stm32-lptim";
300 #address-cells = <1>;
301 #size-cells = <0>;
304 interrupt-names = "wakeup";
309 compatible = "st,stm32-adc";
314 #io-channel-cells = <1>;
319 sampling-times = <2 4 8 13 20 40 80 161>;
320 num-sampling-time-common-channels = <1>;
321 st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
322 st,adc-oversampler = "OVERSAMPLER_MINIMAL";
325 dma1: dma@40020000 {
326 compatible = "st,stm32-dma-v2";
327 #dma-cells = <3>;
335 compatible = "st,stm32-eeprom";
341 compatible = "st,stm32-temp-cal";
342 ts-cal1-addr = <0x1FF8007A>;
343 ts-cal2-addr = <0x1FF8007E>;
344 ts-cal1-temp = <30>;
345 ts-cal2-temp = <130>;
346 ts-cal-vrefanalog = <3000>;
347 io-channels = <&adc1 18>;
352 compatible = "st,stm32-vref";
353 vrefint-cal-addr = <0x1FF80078>;
354 vrefint-cal-mv = <3000>;
355 io-channels = <&adc1 17>;
360 compatible = "st,stm32-smbus";
361 #address-cells = <1>;
362 #size-cells = <0>;
369 arm,num-irq-priority-bits = <2>;