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Searched refs:Bank (Results 1 – 25 of 68) sorted by relevance

123

/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_fmc.c293 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FMC_NORSRAM_DeInit() argument
298 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_DeInit()
301 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
305 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
307 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
312 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
315 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
316 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
330 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
343 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_fmc.c288 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FMC_NORSRAM_DeInit() argument
293 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_DeInit()
296 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
300 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
302 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
307 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
310 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
311 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
325 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
338 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_fmc.c288 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FMC_NORSRAM_DeInit() argument
293 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_DeInit()
296 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
300 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
302 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
307 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
310 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
311 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
325 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
338 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_Timing_Init()
[all …]
Dstm32h7xx_hal_flash_ex.c116 static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank);
117 static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank);
121 …OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAddr, uint32_t Bank);
129 …32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank);
130 static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank);
131 static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank);
716 assert_param(IS_FLASH_BANK_EXCLUSIVE(pCRCInit->Bank)); in HAL_FLASHEx_ComputeCRC()
724 if (pCRCInit->Bank == FLASH_BANK_1) in HAL_FLASHEx_ComputeCRC()
1311 static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank) in FLASH_OB_GetWRP() argument
1315 if(Bank == FLASH_BANK_1) in FLASH_OB_GetWRP()
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_fmc.c281 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FMC_NORSRAM_DeInit() argument
286 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_DeInit()
289 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
293 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
295 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
300 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
303 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
304 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
318 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
332 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_fmc.c329 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FMC_NORSRAM_DeInit() argument
334 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_DeInit()
337 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
341 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
343 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
348 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
351 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
352 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
355 switch (Bank) in FMC_NORSRAM_DeInit()
386 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
[all …]
Dstm32h5xx_hal_flash_ex.c113 static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank);
114 static void FLASH_OB_GetWRP(uint32_t Bank, uint32_t *WRPState, uint32_t *WRPSector);
125 static void FLASH_OB_GetHDP(uint32_t Bank, uint32_t *HDPStartSector, uint32_t *HDPEndSector);
128 static void FLASH_OB_GetEDATA(uint32_t Bank, uint32_t *EDATASize);
132 static void FLASH_OB_GetWMSEC(uint32_t Bank, uint32_t *WMSecStartSector, uint32_t *WMSecEndSector);
278 pFlash.Bank = pEraseInit->Banks; in HAL_FLASHEx_Erase_IT()
685 assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank)); in HAL_FLASHEx_ConfigBBAttributes()
697 if (pBBAttributes->Bank == FLASH_BANK_1) in HAL_FLASHEx_ConfigBBAttributes()
709 if (pBBAttributes->Bank == FLASH_BANK_1) in HAL_FLASHEx_ConfigBBAttributes()
758 assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank)); in HAL_FLASHEx_GetConfigBBAttributes()
[all …]
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_fmc.c362 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FMC_NORSRAM_DeInit() argument
367 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_DeInit()
370 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
374 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
376 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
381 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
384 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
385 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
399 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
414 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_Timing_Init()
[all …]
Dstm32f4xx_ll_fsmc.c343 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FSMC_NORSRAM_DeInit() argument
348 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); in FSMC_NORSRAM_DeInit()
351 __FSMC_NORSRAM_DISABLE(Device, Bank); in FSMC_NORSRAM_DeInit()
355 if (Bank == FSMC_NORSRAM_BANK1) in FSMC_NORSRAM_DeInit()
357 Device->BTCR[Bank] = 0x000030DBU; in FSMC_NORSRAM_DeInit()
362 Device->BTCR[Bank] = 0x000030D2U; in FSMC_NORSRAM_DeInit()
365 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
366 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
380 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FSMC_NORSRAM_Timing_Init() argument
395 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); in FSMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_fmc.c341 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FMC_NORSRAM_DeInit() argument
346 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_DeInit()
349 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
353 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
355 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
360 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
363 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
364 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
368 switch (Bank) in FMC_NORSRAM_DeInit()
400 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
[all …]
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_fmc.c305 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FMC_NORSRAM_DeInit() argument
310 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_DeInit()
313 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
317 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
319 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
324 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
327 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
328 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
331 switch (Bank) in FMC_NORSRAM_DeInit()
362 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
[all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_fmc.c310 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FMC_NORSRAM_DeInit() argument
315 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_DeInit()
318 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
322 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
324 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
329 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
332 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
333 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
336 switch (Bank) in FMC_NORSRAM_DeInit()
367 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
[all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_fmc.c310 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FMC_NORSRAM_DeInit() argument
315 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_DeInit()
318 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
322 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
324 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
329 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
332 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
333 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
336 switch (Bank) in FMC_NORSRAM_DeInit()
367 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
[all …]
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_fsmc.c292 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FSMC_NORSRAM_DeInit() argument
297 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); in FSMC_NORSRAM_DeInit()
300 __FSMC_NORSRAM_DISABLE(Device, Bank); in FSMC_NORSRAM_DeInit()
304 if (Bank == FSMC_NORSRAM_BANK1) in FSMC_NORSRAM_DeInit()
306 Device->BTCR[Bank] = 0x000030DBU; in FSMC_NORSRAM_DeInit()
311 Device->BTCR[Bank] = 0x000030D2U; in FSMC_NORSRAM_DeInit()
314 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
315 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
329 const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FSMC_NORSRAM_Timing_Init() argument
341 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); in FSMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_ll_fsmc.c276 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FSMC_NORSRAM_DeInit() argument
281 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); in FSMC_NORSRAM_DeInit()
284 __FSMC_NORSRAM_DISABLE(Device, Bank); in FSMC_NORSRAM_DeInit()
288 if (Bank == FSMC_NORSRAM_BANK1) in FSMC_NORSRAM_DeInit()
290 Device->BTCR[Bank] = 0x000030DBU; in FSMC_NORSRAM_DeInit()
295 Device->BTCR[Bank] = 0x000030D2U; in FSMC_NORSRAM_DeInit()
298 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
299 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
313 const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FSMC_NORSRAM_Timing_Init() argument
325 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); in FSMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_fmc.c290 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FMC_NORSRAM_DeInit() argument
295 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_DeInit()
298 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
302 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
304 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
309 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
312 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
313 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
327 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
340 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/src/
Dstm32l1xx_ll_fsmc.c239 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FSMC_NORSRAM_DeInit() argument
244 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); in FSMC_NORSRAM_DeInit()
247 __FSMC_NORSRAM_DISABLE(Device, Bank); in FSMC_NORSRAM_DeInit()
251 if (Bank == FSMC_NORSRAM_BANK1) in FSMC_NORSRAM_DeInit()
253 Device->BTCR[Bank] = 0x000030DBU; in FSMC_NORSRAM_DeInit()
258 Device->BTCR[Bank] = 0x000030D2U; in FSMC_NORSRAM_DeInit()
261 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
262 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
276 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FSMC_NORSRAM_Timing_Init() argument
288 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); in FSMC_NORSRAM_Timing_Init()
[all …]
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_fmc.c276 …_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) in FMC_NORSRAM_DeInit() argument
281 assert_param(IS_FMC_NORSRAM_BANK(Bank)); in FMC_NORSRAM_DeInit()
284 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
288 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
290 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
295 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
298 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
299 ExDevice->BWTR[Bank] = 0x000FFFFFU; in FMC_NORSRAM_DeInit()
302 switch (Bank) in FMC_NORSRAM_DeInit()
335 …_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
[all …]
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_fmc.h1050 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1052 … FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
1055 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1063 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1064 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1080 … FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1082 … FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1083 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1091 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1092 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_fmc.h1062 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1064 … const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
1067 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1075 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1076 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1092 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1094 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1095 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1103 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1104 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
[all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_fmc.h1062 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1064 … const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
1067 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1075 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1076 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1092 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1094 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1095 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1103 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1104 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_fmc.h1062 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1064 … const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
1067 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1075 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1076 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1092 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1094 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1095 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1103 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1104 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_fmc.h1143 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1145 … const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
1148 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1156 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1157 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1175 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1177 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1178 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1186 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1187 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
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/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_fmc.h1288 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1290 … FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
1293 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1301 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1302 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1320 … FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1322 … FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1323 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1331 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1332 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
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/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_fsmc.h807 … const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
809 … const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
812 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
820 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
821 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
837 … const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
839 … const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
840 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
848 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
849 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
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