1 /** 2 ****************************************************************************** 3 * @file stm32f2xx_ll_fsmc.h 4 * @author MCD Application Team 5 * @brief Header file of FSMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F2xx_LL_FSMC_H 21 #define STM32F2xx_LL_FSMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f2xx_hal_def.h" 29 30 /** @addtogroup STM32F2xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FSMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FSMC_LL_Private_Macros 39 * @{ 40 */ 41 42 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ 43 ((__BANK__) == FSMC_NORSRAM_BANK2) || \ 44 ((__BANK__) == FSMC_NORSRAM_BANK3) || \ 45 ((__BANK__) == FSMC_NORSRAM_BANK4)) 46 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ 47 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) 48 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ 49 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ 50 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) 51 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 52 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 53 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) 54 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ 55 ((__MODE__) == FSMC_ACCESS_MODE_B) || \ 56 ((__MODE__) == FSMC_ACCESS_MODE_C) || \ 57 ((__MODE__) == FSMC_ACCESS_MODE_D)) 58 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ 59 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) 60 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ 61 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) 62 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ 63 ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) 64 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ 65 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) 66 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ 67 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) 68 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ 69 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) 70 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ 71 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) 72 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 73 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) 74 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 75 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ 76 ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) 77 #define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 78 ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 79 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 80 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 81 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 82 #define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 83 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 84 #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 85 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) 86 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) 87 88 89 #define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3) 90 #define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ 91 ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) 92 #define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ 93 ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) 94 #define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \ 95 ((__STATE__) == FSMC_NAND_ECC_ENABLE)) 96 97 #define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 98 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 99 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 100 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 101 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 102 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 103 #define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 104 #define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 105 #define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 106 #define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 107 #define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 108 #define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 109 #define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE) 110 111 #define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE) 112 113 114 /** 115 * @} 116 */ 117 118 /* Exported typedef ----------------------------------------------------------*/ 119 120 /** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types 121 * @{ 122 */ 123 124 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef 125 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef 126 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef 127 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef 128 129 #define FSMC_NORSRAM_DEVICE FSMC_Bank1 130 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E 131 #define FSMC_NAND_DEVICE FSMC_Bank2_3 132 #define FSMC_PCCARD_DEVICE FSMC_Bank4 133 134 /** 135 * @brief FSMC NORSRAM Configuration Structure definition 136 */ 137 typedef struct 138 { 139 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 140 This parameter can be a value of @ref FSMC_NORSRAM_Bank */ 141 142 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 143 multiplexed on the data bus or not. 144 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing*/ 145 146 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 147 the corresponding memory device. 148 This parameter can be a value of @ref FSMC_Memory_Type */ 149 150 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 151 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ 152 153 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 154 valid only with synchronous burst Flash memories. 155 This parameter can be a value of @ref FSMC_Burst_Access_Mode */ 156 157 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 158 the Flash memory in burst mode. 159 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ 160 161 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash 162 memory, valid only when accessing Flash memories in burst mode. 163 This parameter can be a value of @ref FSMC_Wrap_Mode */ 164 165 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 166 clock cycle before the wait state or during the wait state, 167 valid only when accessing memories in burst mode. 168 This parameter can be a value of @ref FSMC_Wait_Timing */ 169 170 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device 171 by the FSMC. 172 This parameter can be a value of @ref FSMC_Write_Operation */ 173 174 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 175 signal, valid for Flash memory access in burst mode. 176 This parameter can be a value of @ref FSMC_Wait_Signal */ 177 178 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 179 This parameter can be a value of @ref FSMC_Extended_Mode */ 180 181 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 182 valid only with asynchronous Flash memories. 183 This parameter can be a value of @ref FSMC_AsynchronousWait */ 184 185 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 186 This parameter can be a value of @ref FSMC_Write_Burst */ 187 188 } FSMC_NORSRAM_InitTypeDef; 189 190 /** 191 * @brief FSMC NORSRAM Timing parameters structure definition 192 */ 193 typedef struct 194 { 195 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 196 the duration of the address setup time. 197 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 198 @note This parameter is not used with synchronous NOR Flash memories. */ 199 200 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 201 the duration of the address hold time. 202 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 203 @note This parameter is not used with synchronous NOR Flash memories. */ 204 205 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 206 the duration of the data setup time. 207 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 208 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 209 NOR Flash memories. */ 210 211 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 212 the duration of the bus turnaround. 213 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 214 @note This parameter is only used for multiplexed NOR Flash memories. */ 215 216 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 217 HCLK cycles. This parameter can be a value between Min_Data = 2 and 218 Max_Data = 16. 219 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 220 accesses. */ 221 222 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 223 to the memory before getting the first data. 224 The parameter value depends on the memory type as shown below: 225 - It must be set to 0 in case of a CRAM 226 - It is don't care in asynchronous NOR, SRAM or ROM accesses 227 - It may assume a value between Min_Data = 2 and Max_Data = 17 228 in NOR Flash memories with synchronous burst mode enable */ 229 230 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 231 This parameter can be a value of @ref FSMC_Access_Mode */ 232 } FSMC_NORSRAM_TimingTypeDef; 233 234 /** 235 * @brief FSMC NAND Configuration Structure definition 236 */ 237 typedef struct 238 { 239 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 240 This parameter can be a value of @ref FSMC_NAND_Bank */ 241 242 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 243 This parameter can be any value of @ref FSMC_Wait_feature */ 244 245 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 246 This parameter can be any value of @ref FSMC_NAND_Data_Width */ 247 248 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 249 This parameter can be any value of @ref FSMC_ECC */ 250 251 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 252 This parameter can be any value of @ref FSMC_ECC_Page_Size */ 253 254 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 255 delay between CLE low and RE low. 256 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 257 258 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 259 delay between ALE low and RE low. 260 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 261 } FSMC_NAND_InitTypeDef; 262 263 /** 264 * @brief FSMC NAND Timing parameters structure definition 265 */ 266 typedef struct 267 { 268 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 269 the command assertion for NAND-Flash read or write access 270 to common/Attribute or I/O memory space (depending on 271 the memory space timing to be configured). 272 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 273 274 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 275 command for NAND-Flash read or write access to 276 common/Attribute or I/O memory space (depending on the 277 memory space timing to be configured). 278 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 279 280 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 281 (and data for write access) after the command de-assertion 282 for NAND-Flash read or write access to common/Attribute 283 or I/O memory space (depending on the memory space timing 284 to be configured). 285 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 286 287 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 288 data bus is kept in HiZ after the start of a NAND-Flash 289 write access to common/Attribute or I/O memory space (depending 290 on the memory space timing to be configured). 291 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 292 } FSMC_NAND_PCC_TimingTypeDef; 293 294 /** 295 * @brief FSMC PCCARD Configuration Structure definition 296 */ 297 typedef struct 298 { 299 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. 300 This parameter can be any value of @ref FSMC_Wait_feature */ 301 302 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 303 delay between CLE low and RE low. 304 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 305 306 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 307 delay between ALE low and RE low. 308 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 309 } FSMC_PCCARD_InitTypeDef; 310 311 /** 312 * @} 313 */ 314 315 /* Exported constants --------------------------------------------------------*/ 316 /** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants 317 * @{ 318 */ 319 320 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller 321 * @{ 322 */ 323 324 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank 325 * @{ 326 */ 327 #define FSMC_NORSRAM_BANK1 (0x00000000U) 328 #define FSMC_NORSRAM_BANK2 (0x00000002U) 329 #define FSMC_NORSRAM_BANK3 (0x00000004U) 330 #define FSMC_NORSRAM_BANK4 (0x00000006U) 331 /** 332 * @} 333 */ 334 335 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing 336 * @{ 337 */ 338 #define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 339 #define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 340 /** 341 * @} 342 */ 343 344 /** @defgroup FSMC_Memory_Type FSMC Memory Type 345 * @{ 346 */ 347 #define FSMC_MEMORY_TYPE_SRAM (0x00000000U) 348 #define FSMC_MEMORY_TYPE_PSRAM (0x00000004U) 349 #define FSMC_MEMORY_TYPE_NOR (0x00000008U) 350 /** 351 * @} 352 */ 353 354 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width 355 * @{ 356 */ 357 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 358 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 359 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 360 /** 361 * @} 362 */ 363 364 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access 365 * @{ 366 */ 367 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 368 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 369 /** 370 * @} 371 */ 372 373 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode 374 * @{ 375 */ 376 #define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 377 #define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 378 /** 379 * @} 380 */ 381 382 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity 383 * @{ 384 */ 385 #define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 386 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 387 /** 388 * @} 389 */ 390 391 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode 392 * @{ 393 */ 394 #define FSMC_WRAP_MODE_DISABLE (0x00000000U) 395 #define FSMC_WRAP_MODE_ENABLE (0x00000400U) 396 /** 397 * @} 398 */ 399 400 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing 401 * @{ 402 */ 403 #define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 404 #define FSMC_WAIT_TIMING_DURING_WS (0x00000800U) 405 /** 406 * @} 407 */ 408 409 /** @defgroup FSMC_Write_Operation FSMC Write Operation 410 * @{ 411 */ 412 #define FSMC_WRITE_OPERATION_DISABLE (0x00000000U) 413 #define FSMC_WRITE_OPERATION_ENABLE (0x00001000U) 414 /** 415 * @} 416 */ 417 418 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal 419 * @{ 420 */ 421 #define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U) 422 #define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U) 423 /** 424 * @} 425 */ 426 427 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode 428 * @{ 429 */ 430 #define FSMC_EXTENDED_MODE_DISABLE (0x00000000U) 431 #define FSMC_EXTENDED_MODE_ENABLE (0x00004000U) 432 /** 433 * @} 434 */ 435 436 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait 437 * @{ 438 */ 439 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 440 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 441 /** 442 * @} 443 */ 444 445 /** @defgroup FSMC_Write_Burst FSMC Write Burst 446 * @{ 447 */ 448 #define FSMC_WRITE_BURST_DISABLE (0x00000000U) 449 #define FSMC_WRITE_BURST_ENABLE (0x00080000U) 450 /** 451 * @} 452 */ 453 454 /** @defgroup FSMC_Continous_Clock FSMC Continuous Clock 455 * @{ 456 */ 457 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 458 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 459 /** 460 * @} 461 */ 462 463 /** @defgroup FSMC_Access_Mode FSMC Access Mode 464 * @{ 465 */ 466 #define FSMC_ACCESS_MODE_A (0x00000000U) 467 #define FSMC_ACCESS_MODE_B (0x10000000U) 468 #define FSMC_ACCESS_MODE_C (0x20000000U) 469 #define FSMC_ACCESS_MODE_D (0x30000000U) 470 /** 471 * @} 472 */ 473 474 /** 475 * @} 476 */ 477 478 479 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller 480 * @{ 481 */ 482 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank 483 * @{ 484 */ 485 #define FSMC_NAND_BANK2 (0x00000010U) 486 #define FSMC_NAND_BANK3 (0x00000100U) 487 /** 488 * @} 489 */ 490 491 /** @defgroup FSMC_Wait_feature FSMC Wait feature 492 * @{ 493 */ 494 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U) 495 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U) 496 /** 497 * @} 498 */ 499 500 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type 501 * @{ 502 */ 503 #define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U) 504 #define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U) 505 /** 506 * @} 507 */ 508 509 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width 510 * @{ 511 */ 512 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U) 513 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U) 514 /** 515 * @} 516 */ 517 518 /** @defgroup FSMC_ECC FSMC ECC 519 * @{ 520 */ 521 #define FSMC_NAND_ECC_DISABLE (0x00000000U) 522 #define FSMC_NAND_ECC_ENABLE (0x00000040U) 523 /** 524 * @} 525 */ 526 527 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size 528 * @{ 529 */ 530 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) 531 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) 532 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) 533 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) 534 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) 535 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) 536 /** 537 * @} 538 */ 539 540 /** 541 * @} 542 */ 543 544 545 /** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition 546 * @{ 547 */ 548 #define FSMC_IT_RISING_EDGE (0x00000008U) 549 #define FSMC_IT_LEVEL (0x00000010U) 550 #define FSMC_IT_FALLING_EDGE (0x00000020U) 551 /** 552 * @} 553 */ 554 555 /** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition 556 * @{ 557 */ 558 #define FSMC_FLAG_RISING_EDGE (0x00000001U) 559 #define FSMC_FLAG_LEVEL (0x00000002U) 560 #define FSMC_FLAG_FALLING_EDGE (0x00000004U) 561 #define FSMC_FLAG_FEMPT (0x00000040U) 562 /** 563 * @} 564 */ 565 566 /** 567 * @} 568 */ 569 570 /** 571 * @} 572 */ 573 574 /* Private macro -------------------------------------------------------------*/ 575 /** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros 576 * @{ 577 */ 578 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros 579 * @brief macros to handle NOR device enable/disable and read/write operations 580 * @{ 581 */ 582 583 /** 584 * @brief Enable the NORSRAM device access. 585 * @param __INSTANCE__ FSMC_NORSRAM Instance 586 * @param __BANK__ FSMC_NORSRAM Bank 587 * @retval None 588 */ 589 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 590 |= FSMC_BCR1_MBKEN) 591 592 /** 593 * @brief Disable the NORSRAM device access. 594 * @param __INSTANCE__ FSMC_NORSRAM Instance 595 * @param __BANK__ FSMC_NORSRAM Bank 596 * @retval None 597 */ 598 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 599 &= ~FSMC_BCR1_MBKEN) 600 601 /** 602 * @} 603 */ 604 605 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros 606 * @brief macros to handle NAND device enable/disable 607 * @{ 608 */ 609 610 /** 611 * @brief Enable the NAND device access. 612 * @param __INSTANCE__ FSMC_NAND Instance 613 * @param __BANK__ FSMC_NAND Bank 614 * @retval None 615 */ 616 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \ 617 ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN) : \ 618 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN)) 619 620 /** 621 * @brief Disable the NAND device access. 622 * @param __INSTANCE__ FSMC_NAND Instance 623 * @param __BANK__ FSMC_NAND Bank 624 * @retval None 625 */ 626 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \ 627 CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCR2_PBKEN) : \ 628 CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN)) 629 630 /** 631 * @} 632 */ 633 634 /** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros 635 * @brief macros to handle PCCARD read/write operations 636 * @{ 637 */ 638 /** 639 * @brief Enable the PCCARD device access. 640 * @param __INSTANCE__ FSMC_PCCARD Instance 641 * @retval None 642 */ 643 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN) 644 645 /** 646 * @brief Disable the PCCARD device access. 647 * @param __INSTANCE__ FSMC_PCCARD Instance 648 * @retval None 649 */ 650 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN) 651 /** 652 * @} 653 */ 654 655 /** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt 656 * @brief macros to handle NAND interrupts 657 * @{ 658 */ 659 660 /** 661 * @brief Enable the NAND device interrupt. 662 * @param __INSTANCE__ FSMC_NAND instance 663 * @param __BANK__ FSMC_NAND Bank 664 * @param __INTERRUPT__ FSMC_NAND interrupt 665 * This parameter can be any combination of the following values: 666 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 667 * @arg FSMC_IT_LEVEL: Interrupt level. 668 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 669 * @retval None 670 */ 671 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \ 672 ((__INSTANCE__)->SR2 |= (__INTERRUPT__)) : \ 673 ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) 674 675 /** 676 * @brief Disable the NAND device interrupt. 677 * @param __INSTANCE__ FSMC_NAND Instance 678 * @param __BANK__ FSMC_NAND Bank 679 * @param __INTERRUPT__ FSMC_NAND interrupt 680 * This parameter can be any combination of the following values: 681 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 682 * @arg FSMC_IT_LEVEL: Interrupt level. 683 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 684 * @retval None 685 */ 686 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \ 687 ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)) : \ 688 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) 689 690 /** 691 * @brief Get flag status of the NAND device. 692 * @param __INSTANCE__ FSMC_NAND Instance 693 * @param __BANK__ FSMC_NAND Bank 694 * @param __FLAG__ FSMC_NAND flag 695 * This parameter can be any combination of the following values: 696 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 697 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 698 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 699 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 700 * @retval The state of FLAG (SET or RESET). 701 */ 702 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \ 703 (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)) : \ 704 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) 705 706 /** 707 * @brief Clear flag status of the NAND device. 708 * @param __INSTANCE__ FSMC_NAND Instance 709 * @param __BANK__ FSMC_NAND Bank 710 * @param __FLAG__ FSMC_NAND flag 711 * This parameter can be any combination of the following values: 712 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 713 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 714 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 715 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 716 * @retval None 717 */ 718 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \ 719 ((__INSTANCE__)->SR2 &= ~(__FLAG__)) : \ 720 ((__INSTANCE__)->SR3 &= ~(__FLAG__))) 721 722 /** 723 * @} 724 */ 725 726 /** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt 727 * @brief macros to handle PCCARD interrupts 728 * @{ 729 */ 730 731 /** 732 * @brief Enable the PCCARD device interrupt. 733 * @param __INSTANCE__ FSMC_PCCARD instance 734 * @param __INTERRUPT__ FSMC_PCCARD interrupt 735 * This parameter can be any combination of the following values: 736 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 737 * @arg FSMC_IT_LEVEL: Interrupt level. 738 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 739 * @retval None 740 */ 741 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) 742 743 /** 744 * @brief Disable the PCCARD device interrupt. 745 * @param __INSTANCE__ FSMC_PCCARD instance 746 * @param __INTERRUPT__ FSMC_PCCARD interrupt 747 * This parameter can be any combination of the following values: 748 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 749 * @arg FSMC_IT_LEVEL: Interrupt level. 750 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 751 * @retval None 752 */ 753 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) 754 755 /** 756 * @brief Get flag status of the PCCARD device. 757 * @param __INSTANCE__ FSMC_PCCARD instance 758 * @param __FLAG__ FSMC_PCCARD flag 759 * This parameter can be any combination of the following values: 760 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 761 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 762 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 763 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 764 * @retval The state of FLAG (SET or RESET). 765 */ 766 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) 767 768 /** 769 * @brief Clear flag status of the PCCARD device. 770 * @param __INSTANCE__ FSMC_PCCARD instance 771 * @param __FLAG__ FSMC_PCCARD flag 772 * This parameter can be any combination of the following values: 773 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 774 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 775 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 776 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 777 * @retval None 778 */ 779 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) 780 781 /** 782 * @} 783 */ 784 785 /** 786 * @} 787 */ 788 789 /** 790 * @} 791 */ 792 793 /* Private functions ---------------------------------------------------------*/ 794 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions 795 * @{ 796 */ 797 798 /** @defgroup FSMC_LL_NORSRAM NOR SRAM 799 * @{ 800 */ 801 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 802 * @{ 803 */ 804 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, 805 const FSMC_NORSRAM_InitTypeDef *Init); 806 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, 807 const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 808 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, 809 const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 810 uint32_t ExtendedMode); 811 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, 812 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 813 /** 814 * @} 815 */ 816 817 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 818 * @{ 819 */ 820 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); 821 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); 822 /** 823 * @} 824 */ 825 /** 826 * @} 827 */ 828 829 /** @defgroup FSMC_LL_NAND NAND 830 * @{ 831 */ 832 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 833 * @{ 834 */ 835 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, const FSMC_NAND_InitTypeDef *Init); 836 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, 837 const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 838 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, 839 const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 840 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); 841 /** 842 * @} 843 */ 844 845 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions 846 * @{ 847 */ 848 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); 849 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); 850 HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, 851 uint32_t Timeout); 852 /** 853 * @} 854 */ 855 /** 856 * @} 857 */ 858 859 /** @defgroup FSMC_LL_PCCARD PCCARD 860 * @{ 861 */ 862 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions 863 * @{ 864 */ 865 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, const FSMC_PCCARD_InitTypeDef *Init); 866 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, 867 const FSMC_NAND_PCC_TimingTypeDef *Timing); 868 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, 869 const FSMC_NAND_PCC_TimingTypeDef *Timing); 870 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, 871 const FSMC_NAND_PCC_TimingTypeDef *Timing); 872 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); 873 /** 874 * @} 875 */ 876 /** 877 * @} 878 */ 879 880 881 /** 882 * @} 883 */ 884 885 /** 886 * @} 887 */ 888 889 /** 890 * @} 891 */ 892 893 #ifdef __cplusplus 894 } 895 #endif 896 897 #endif /* STM32F2xx_LL_FSMC_H */ 898
