1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_fmc.c
4 * @author MCD Application Team
5 * @brief FMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2020 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### FMC peripheral features #####
27 ==============================================================================
28 [..] The Flexible memory controller (FMC) includes following memory controllers:
29 (+) The NOR/PSRAM memory controller
30 (+) The NAND memory controller
31 (+) The Synchronous DRAM (SDRAM) controller
32
33 [..] The FMC functional block makes the interface with synchronous and asynchronous static
34 memories and SDRAM memories. Its main purposes are:
35 (+) to translate AHB transactions into the appropriate external device protocol
36 (+) to meet the access time requirements of the external memory devices
37
38 [..] All external memories share the addresses, data and control signals with the controller.
39 Each external device is accessed by means of a unique Chip Select. The FMC performs
40 only one access at a time to an external device.
41 The main features of the FMC controller are the following:
42 (+) Interface with static-memory mapped devices including:
43 (++) Static random access memory (SRAM)
44 (++) Read-only memory (ROM)
45 (++) NOR Flash memory/OneNAND Flash memory
46 (++) PSRAM (4 memory banks)
47 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
48 data
49 (+) Interface with synchronous DRAM (SDRAM) memories
50 (+) Independent Chip Select control for each memory bank
51 (+) Independent configuration for each memory bank
52
53 @endverbatim
54 ******************************************************************************
55 */
56
57 /* Includes ------------------------------------------------------------------*/
58 #include "stm32n6xx_hal.h"
59
60 /** @addtogroup STM32N6xx_HAL_Driver
61 * @{
62 */
63 #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\
64 || defined(HAL_SRAM_MODULE_ENABLED)
65
66 /** @defgroup FMC_LL FMC Low Layer
67 * @brief FMC driver modules
68 * @{
69 */
70
71 /* Private typedef -----------------------------------------------------------*/
72 /* Private define ------------------------------------------------------------*/
73
74 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
75 * @{
76 */
77
78 /* ----------------------- FMC registers bit mask --------------------------- */
79
80 /* --- BCR Register ---*/
81 /* BCR register clear mask */
82
83 /* --- BTR Register ---*/
84 /* BTR register clear mask */
85 #define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
86 FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
87 FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
88 FMC_BTRx_ACCMOD | FMC_BTRx_DATAHLD))
89
90 /* --- BWTR Register ---*/
91 /* BWTR register clear mask */
92 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
93 FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
94 FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD))
95
96 /* --- PCR Register ---*/
97 /* PCR register clear mask */
98 #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \
99 FMC_PCR_PWID | FMC_PCR_ECCEN | \
100 FMC_PCR_TCLR | FMC_PCR_TAR | \
101 FMC_PCR_ECCSS))
102 /* --- PMEM Register ---*/
103 /* PMEM register clear mask */
104 #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\
105 FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ))
106
107 /* --- PATT Register ---*/
108 /* PATT register clear mask */
109 #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\
110 FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ))
111
112
113 /* --- SDCR Register ---*/
114 /* SDCR register clear mask */
115 #define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCRx_NC | FMC_SDCRx_NR | \
116 FMC_SDCRx_MWID | FMC_SDCRx_NB | \
117 FMC_SDCRx_CAS | FMC_SDCRx_WP | \
118 FMC_SDCRx_SDCLK | FMC_SDCRx_RPIPE))
119
120 /* --- SDTR Register ---*/
121 /* SDTR register clear mask */
122 #define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTRx_TMRD | FMC_SDTRx_TXSR | \
123 FMC_SDTRx_TRAS | FMC_SDTRx_TRC | \
124 FMC_SDTRx_TWR | FMC_SDTRx_TRP | \
125 FMC_SDTRx_TRCD))
126
127 /**
128 * @}
129 */
130
131 /* Private macro -------------------------------------------------------------*/
132 /* Private variables ---------------------------------------------------------*/
133 /* Private function prototypes -----------------------------------------------*/
134 /* Exported functions --------------------------------------------------------*/
135
136 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
137 * @{
138 */
139
140
141 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
142 * @brief NORSRAM Controller functions
143 *
144 @verbatim
145 ==============================================================================
146 ##### How to use NORSRAM device driver #####
147 ==============================================================================
148
149 [..]
150 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
151 to run the NORSRAM external devices.
152
153 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
154 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
155 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
156 (+) FMC NORSRAM bank extended timing configuration using the function
157 FMC_NORSRAM_Extended_Timing_Init()
158 (+) FMC NORSRAM bank enable/disable write operation using the functions
159 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
160
161 @endverbatim
162 * @{
163 */
164
165 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
166 * @brief Initialization and Configuration functions
167 *
168 @verbatim
169 ==============================================================================
170 ##### Initialization and de_initialization functions #####
171 ==============================================================================
172 [..]
173 This section provides functions allowing to:
174 (+) Initialize and configure the FMC NORSRAM interface
175 (+) De-initialize the FMC NORSRAM interface
176 (+) Configure the FMC clock and associated GPIOs
177
178 @endverbatim
179 * @{
180 */
181
182 /**
183 * @brief Initialize the FMC_NORSRAM device according to the specified
184 * control parameters in the FMC_NORSRAM_InitTypeDef
185 * @param Device Pointer to NORSRAM device instance
186 * @param Init Pointer to NORSRAM Initialization structure
187 * @retval HAL status
188 */
FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef * Device,const FMC_NORSRAM_InitTypeDef * Init)189 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
190 const FMC_NORSRAM_InitTypeDef *Init)
191 {
192 uint32_t flashaccess;
193 uint32_t btcr_reg;
194 uint32_t mask;
195
196 /* Check the parameters */
197 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
198 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
199 assert_param(IS_FMC_MUX(Init->DataAddressMux));
200 assert_param(IS_FMC_MEMORY(Init->MemoryType));
201 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
202 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
203 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
204 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
205 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
206 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
207 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
208 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
209 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
210 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
211 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
212 assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime));
213
214 /* Disable NORSRAM Device */
215 __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
216
217 /* Set NORSRAM device control parameters */
218 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
219 {
220 flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
221 }
222 else
223 {
224 flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
225 }
226
227 btcr_reg = (flashaccess | \
228 Init->DataAddressMux | \
229 Init->MemoryType | \
230 Init->MemoryDataWidth | \
231 Init->BurstAccessMode | \
232 Init->WaitSignalPolarity | \
233 Init->WaitSignalActive | \
234 Init->WriteOperation | \
235 Init->WaitSignal | \
236 Init->ExtendedMode | \
237 Init->AsynchronousWait | \
238 Init->WriteBurst);
239
240 btcr_reg |= Init->ContinuousClock;
241 btcr_reg |= Init->NBLSetupTime;
242 btcr_reg |= Init->PageSize;
243
244 mask = (FMC_BCRx_MBKEN |
245 FMC_BCRx_MUXEN |
246 FMC_BCRx_MTYP |
247 FMC_BCRx_MWID |
248 FMC_BCRx_FACCEN |
249 FMC_BCRx_BURSTEN |
250 FMC_BCRx_WAITPOL |
251 FMC_BCRx_WAITCFG |
252 FMC_BCRx_WREN |
253 FMC_BCRx_WAITEN |
254 FMC_BCRx_EXTMOD |
255 FMC_BCRx_ASYNCWAIT |
256 FMC_BCRx_CBURSTRW);
257
258 mask |= FMC_CFGR_CCLKEN;
259 mask |= FMC_BCRx_NBLSET;
260 mask |= FMC_BCRx_CPSIZE;
261
262 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
263
264 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
265 if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
266 {
267 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_CFGR_CCLKEN, Init->ContinuousClock);
268 }
269
270 return HAL_OK;
271 }
272
273 /**
274 * @brief DeInitialize the FMC_NORSRAM peripheral
275 * @param Device Pointer to NORSRAM device instance
276 * @param ExDevice Pointer to NORSRAM extended mode device instance
277 * @param Bank NORSRAM bank number
278 * @retval HAL status
279 */
FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_EXTENDED_TypeDef * ExDevice,uint32_t Bank)280 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
281 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
282 {
283 /* Check the parameters */
284 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
285 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
286 assert_param(IS_FMC_NORSRAM_BANK(Bank));
287
288 /* Disable the FMC_NORSRAM device */
289 __FMC_NORSRAM_DISABLE(Device, Bank);
290
291 /* De-initialize the FMC_NORSRAM device */
292 /* FMC_NORSRAM_BANK1 */
293 if (Bank == FMC_NORSRAM_BANK1)
294 {
295 Device->BTCR[Bank] = 0x000030DBU;
296 }
297 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
298 else
299 {
300 Device->BTCR[Bank] = 0x000030D2U;
301 }
302
303 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
304 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
305
306 return HAL_OK;
307 }
308
309 /**
310 * @brief Initialize the FMC_NORSRAM Timing according to the specified
311 * parameters in the FMC_NORSRAM_TimingTypeDef
312 * @param Device Pointer to NORSRAM device instance
313 * @param Timing Pointer to NORSRAM Timing structure
314 * @param Bank NORSRAM bank number
315 * @retval HAL status
316 */
FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef * Device,const FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank)317 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
318 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
319 {
320 uint32_t tmpr;
321
322 /* Check the parameters */
323 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
324 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
325 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
326 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
327 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
328 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
329 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
330 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
331 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
332 assert_param(IS_FMC_NORSRAM_BANK(Bank));
333
334 /* Set FMC_NORSRAM device timing parameters */
335 Device->BTCR[Bank + 1U] =
336 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) |
337 (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) |
338 (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) |
339 (Timing->DataHoldTime << FMC_BTRx_DATAHLD_Pos) |
340 (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) |
341 ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) |
342 ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) |
343 Timing->AccessMode;
344
345 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
346 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_CFGR_CCLKEN))
347 {
348 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));
349 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos);
350 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);
351 }
352
353 return HAL_OK;
354 }
355
356 /**
357 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
358 * parameters in the FMC_NORSRAM_TimingTypeDef
359 * @param Device Pointer to NORSRAM device instance
360 * @param Timing Pointer to NORSRAM Timing structure
361 * @param Bank NORSRAM bank number
362 * @param ExtendedMode FMC Extended Mode
363 * This parameter can be one of the following values:
364 * @arg FMC_EXTENDED_MODE_DISABLE
365 * @arg FMC_EXTENDED_MODE_ENABLE
366 * @retval HAL status
367 */
FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef * Device,const FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank,uint32_t ExtendedMode)368 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
369 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
370 uint32_t ExtendedMode)
371 {
372 /* Check the parameters */
373 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
374
375 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
376 if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
377 {
378 /* Check the parameters */
379 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
380 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
381 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
382 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
383 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
384 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
385 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
386 assert_param(IS_FMC_NORSRAM_BANK(Bank));
387
388 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
389 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
390 ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) |
391 ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) |
392 ((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) |
393 Timing->AccessMode |
394 ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos)));
395 }
396 else
397 {
398 Device->BWTR[Bank] = 0x0FFFFFFFU;
399 }
400
401 return HAL_OK;
402 }
403 /**
404 * @}
405 */
406
407 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
408 * @brief management functions
409 *
410 @verbatim
411 ==============================================================================
412 ##### FMC_NORSRAM Control functions #####
413 ==============================================================================
414 [..]
415 This subsection provides a set of functions allowing to control dynamically
416 the FMC NORSRAM interface.
417
418 @endverbatim
419 * @{
420 */
421
422 /**
423 * @brief Enables dynamically FMC_NORSRAM write operation.
424 * @param Device Pointer to NORSRAM device instance
425 * @param Bank NORSRAM bank number
426 * @retval HAL status
427 */
FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)428 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
429 {
430 /* Check the parameters */
431 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
432 assert_param(IS_FMC_NORSRAM_BANK(Bank));
433
434 /* Enable write operation */
435 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
436
437 return HAL_OK;
438 }
439
440 /**
441 * @brief Disables dynamically FMC_NORSRAM write operation.
442 * @param Device Pointer to NORSRAM device instance
443 * @param Bank NORSRAM bank number
444 * @retval HAL status
445 */
FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)446 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
447 {
448 /* Check the parameters */
449 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
450 assert_param(IS_FMC_NORSRAM_BANK(Bank));
451
452 /* Disable write operation */
453 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
454
455 return HAL_OK;
456 }
457
458 /**
459 * @}
460 */
461
462 /**
463 * @}
464 */
465
466
467 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
468 * @brief NAND Controller functions
469 *
470 @verbatim
471 ==============================================================================
472 ##### How to use NAND device driver #####
473 ==============================================================================
474 [..]
475 This driver contains a set of APIs to interface with the FMC NAND banks in order
476 to run the NAND external devices.
477
478 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
479 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
480 (+) FMC NAND bank common space timing configuration using the function
481 FMC_NAND_CommonSpace_Timing_Init()
482 (+) FMC NAND bank attribute space timing configuration using the function
483 FMC_NAND_AttributeSpace_Timing_Init()
484 (+) FMC NAND bank enable/disable ECC correction feature using the functions
485 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
486 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
487
488 @endverbatim
489 * @{
490 */
491
492 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
493 * @brief Initialization and Configuration functions
494 *
495 @verbatim
496 ==============================================================================
497 ##### Initialization and de_initialization functions #####
498 ==============================================================================
499 [..]
500 This section provides functions allowing to:
501 (+) Initialize and configure the FMC NAND interface
502 (+) De-initialize the FMC NAND interface
503 (+) Configure the FMC clock and associated GPIOs
504
505 @endverbatim
506 * @{
507 */
508
509 /**
510 * @brief Initializes the FMC_NAND device according to the specified
511 * control parameters in the FMC_NAND_HandleTypeDef
512 * @param Device Pointer to NAND device instance
513 * @param Init Pointer to NAND Initialization structure
514 * @retval HAL status
515 */
FMC_NAND_Init(FMC_NAND_TypeDef * Device,const FMC_NAND_InitTypeDef * Init)516 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init)
517 {
518 /* Check the parameters */
519 assert_param(IS_FMC_NAND_DEVICE(Device));
520 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
521 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
522 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
523 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
524 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
525 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
526 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
527
528 /* NAND bank 3 registers configuration */
529 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |
530 FMC_PCR_MEMORY_TYPE_NAND |
531 Init->MemoryDataWidth |
532 Init->EccComputation |
533 Init->ECCPageSize |
534 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) |
535 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos)));
536
537 return HAL_OK;
538 }
539
540 /**
541 * @brief Initializes the FMC_NAND Common space Timing according to the specified
542 * parameters in the FMC_NAND_PCC_TimingTypeDef
543 * @param Device Pointer to NAND device instance
544 * @param Timing Pointer to NAND timing structure
545 * @param Bank NAND bank number
546 * @retval HAL status
547 */
FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef * Device,const FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)548 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
549 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
550 {
551 /* Check the parameters */
552 assert_param(IS_FMC_NAND_DEVICE(Device));
553 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
554 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
555 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
556 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
557 assert_param(IS_FMC_NAND_BANK(Bank));
558
559 /* Prevent unused argument(s) compilation warning if no assert_param check */
560 UNUSED(Bank);
561
562 /* NAND bank 3 registers configuration */
563 Device->PMEM = (Timing->SetupTime |
564 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
565 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) |
566 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos));
567
568 return HAL_OK;
569 }
570
571 /**
572 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
573 * parameters in the FMC_NAND_PCC_TimingTypeDef
574 * @param Device Pointer to NAND device instance
575 * @param Timing Pointer to NAND timing structure
576 * @param Bank NAND bank number
577 * @retval HAL status
578 */
FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef * Device,const FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)579 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
580 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
581 {
582 /* Check the parameters */
583 assert_param(IS_FMC_NAND_DEVICE(Device));
584 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
585 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
586 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
587 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
588 assert_param(IS_FMC_NAND_BANK(Bank));
589
590 /* Prevent unused argument(s) compilation warning if no assert_param check */
591 UNUSED(Bank);
592
593 /* NAND bank 3 registers configuration */
594 Device->PATT = (Timing->SetupTime |
595 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
596 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
597 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos));
598
599 return HAL_OK;
600 }
601
602 /**
603 * @brief DeInitializes the FMC_NAND device
604 * @param Device Pointer to NAND device instance
605 * @param Bank NAND bank number
606 * @retval HAL status
607 */
FMC_NAND_DeInit(FMC_NAND_TypeDef * Device,uint32_t Bank)608 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
609 {
610 /* Check the parameters */
611 assert_param(IS_FMC_NAND_DEVICE(Device));
612 assert_param(IS_FMC_NAND_BANK(Bank));
613
614 /* Disable the NAND Bank */
615 __FMC_NAND_DISABLE(Device, Bank);
616
617 /* De-initialize the NAND Bank */
618 /* Prevent unused argument(s) compilation warning if no assert_param check */
619 UNUSED(Bank);
620
621 /* Set the FMC_NAND_BANK3 registers to their reset values */
622 WRITE_REG(Device->PCR, 0x0007FE08U);
623 WRITE_REG(Device->SR, 0x00015753U);
624 WRITE_REG(Device->PMEM, 0x0A0A0A0AU);
625 WRITE_REG(Device->PATT, 0x0A0A0A0AU);
626
627 return HAL_OK;
628 }
629
630 /**
631 * @}
632 */
633
634 /** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
635 * @brief management functions
636 *
637 @verbatim
638 ==============================================================================
639 ##### FMC_NAND Control functions #####
640 ==============================================================================
641 [..]
642 This subsection provides a set of functions allowing to control dynamically
643 the FMC NAND interface.
644
645 @endverbatim
646 * @{
647 */
648
649
650 /**
651 * @brief Enables dynamically FMC_NAND ECC feature.
652 * @param Device Pointer to NAND device instance
653 * @param Bank NAND bank number
654 * @retval HAL status
655 */
FMC_NAND_ECC_Enable(FMC_NAND_TypeDef * Device,uint32_t Bank)656 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
657 {
658 /* Check the parameters */
659 assert_param(IS_FMC_NAND_DEVICE(Device));
660 assert_param(IS_FMC_NAND_BANK(Bank));
661
662 /* Enable ECC feature */
663 /* Prevent unused argument(s) compilation warning if no assert_param check */
664 UNUSED(Bank);
665
666 SET_BIT(Device->PCR, FMC_PCR_ECCEN);
667
668 return HAL_OK;
669 }
670
671
672 /**
673 * @brief Disables dynamically FMC_NAND ECC feature.
674 * @param Device Pointer to NAND device instance
675 * @param Bank NAND bank number
676 * @retval HAL status
677 */
FMC_NAND_ECC_Disable(FMC_NAND_TypeDef * Device,uint32_t Bank)678 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
679 {
680 /* Check the parameters */
681 assert_param(IS_FMC_NAND_DEVICE(Device));
682 assert_param(IS_FMC_NAND_BANK(Bank));
683
684 /* Disable ECC feature */
685 /* Prevent unused argument(s) compilation warning if no assert_param check */
686 UNUSED(Bank);
687
688 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
689
690 return HAL_OK;
691 }
692
693 /**
694 * @brief Disables dynamically FMC_NAND ECC feature.
695 * @param Device Pointer to NAND device instance
696 * @param ECCval Pointer to ECC value
697 * @param Bank NAND bank number
698 * @param Timeout Timeout wait value
699 * @retval HAL status
700 */
FMC_NAND_GetECC(const FMC_NAND_TypeDef * Device,uint32_t * ECCval,uint32_t Bank,uint32_t Timeout)701 HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
702 uint32_t Timeout)
703 {
704 uint32_t tickstart;
705
706 /* Check the parameters */
707 assert_param(IS_FMC_NAND_DEVICE(Device));
708 assert_param(IS_FMC_NAND_BANK(Bank));
709
710 /* Get tick */
711 tickstart = HAL_GetTick();
712
713 /* Wait until FIFO is empty */
714 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
715 {
716 /* Check for the Timeout */
717 if (Timeout != HAL_MAX_DELAY)
718 {
719 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
720 {
721 return HAL_TIMEOUT;
722 }
723 }
724 }
725
726 /* Prevent unused argument(s) compilation warning if no assert_param check */
727 UNUSED(Bank);
728
729 /* Get the ECCR register value */
730 *ECCval = (uint32_t)Device->HECCR;
731
732 return HAL_OK;
733 }
734
735 /**
736 * @}
737 */
738
739
740 /** @defgroup FMC_LL_SDRAM
741 * @brief SDRAM Controller functions
742 *
743 @verbatim
744 ==============================================================================
745 ##### How to use SDRAM device driver #####
746 ==============================================================================
747 [..]
748 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
749 to run the SDRAM external devices.
750
751 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
752 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
753 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
754 (+) FMC SDRAM bank enable/disable write operation using the functions
755 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
756 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
757
758 @endverbatim
759 * @{
760 */
761
762 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
763 * @brief Initialization and Configuration functions
764 *
765 @verbatim
766 ==============================================================================
767 ##### Initialization and de_initialization functions #####
768 ==============================================================================
769 [..]
770 This section provides functions allowing to:
771 (+) Initialize and configure the FMC SDRAM interface
772 (+) De-initialize the FMC SDRAM interface
773 (+) Configure the FMC clock and associated GPIOs
774
775 @endverbatim
776 * @{
777 */
778
779 /**
780 * @brief Initializes the FMC_SDRAM device according to the specified
781 * control parameters in the FMC_SDRAM_InitTypeDef
782 * @param Device Pointer to SDRAM device instance
783 * @param Init Pointer to SDRAM Initialization structure
784 * @retval HAL status
785 */
FMC_SDRAM_Init(FMC_SDRAM_TypeDef * Device,const FMC_SDRAM_InitTypeDef * Init)786 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init)
787 {
788 /* Check the parameters */
789 assert_param(IS_FMC_SDRAM_DEVICE(Device));
790 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
791 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
792 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
793 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
794 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
795 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
796 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
797 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
798 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
799
800 /* Set SDRAM bank configuration parameters */
801 if (Init->SDBank == FMC_SDRAM_BANK1)
802 {
803 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
804 SDCR_CLEAR_MASK,
805 (Init->ColumnBitsNumber |
806 Init->RowBitsNumber |
807 Init->MemoryDataWidth |
808 Init->InternalBankNumber |
809 Init->CASLatency |
810 Init->WriteProtection |
811 Init->SDClockPeriod |
812 Init->ReadPipeDelay));
813 }
814 else /* FMC_Bank2_SDRAM */
815 {
816 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
817 FMC_SDCRx_SDCLK |
818 FMC_SDCRx_RPIPE,
819 (Init->SDClockPeriod |
820 Init->ReadPipeDelay));
821
822 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
823 SDCR_CLEAR_MASK,
824 (Init->ColumnBitsNumber |
825 Init->RowBitsNumber |
826 Init->MemoryDataWidth |
827 Init->InternalBankNumber |
828 Init->CASLatency |
829 Init->WriteProtection));
830 }
831
832 return HAL_OK;
833 }
834
835
836 /**
837 * @brief Initializes the FMC_SDRAM device timing according to the specified
838 * parameters in the FMC_SDRAM_TimingTypeDef
839 * @param Device Pointer to SDRAM device instance
840 * @param Timing Pointer to SDRAM Timing structure
841 * @param Bank SDRAM bank number
842 * @retval HAL status
843 */
FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef * Device,const FMC_SDRAM_TimingTypeDef * Timing,uint32_t Bank)844 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
845 const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
846 {
847 /* Check the parameters */
848 assert_param(IS_FMC_SDRAM_DEVICE(Device));
849 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
850 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
851 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
852 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
853 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
854 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
855 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
856 assert_param(IS_FMC_SDRAM_BANK(Bank));
857
858 /* Set SDRAM device timing parameters */
859 MODIFY_REG(Device->SDTR,
860 SDTR_CLEAR_MASK,
861 (((Timing->LoadToActiveDelay) - 1U) |
862 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) |
863 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) |
864 (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) |
865 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) |
866 (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos) |
867 (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos)));
868
869 return HAL_OK;
870 }
871
872 /**
873 * @brief DeInitializes the FMC_SDRAM peripheral
874 * @param Device Pointer to SDRAM device instance
875 * @retval HAL status
876 */
FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef * Device,uint32_t Bank)877 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
878 {
879 /* Check the parameters */
880 assert_param(IS_FMC_SDRAM_DEVICE(Device));
881 assert_param(IS_FMC_SDRAM_BANK(Bank));
882
883 /* De-initialize the SDRAM device */
884 Device->SDCR[Bank] = 0x000002D0U;
885 Device->SDTR = 0x0FFFFFFFU;
886 Device->SDCMR = 0x00000000U;
887 Device->SDRTR = 0x00000000U;
888 Device->SDSR = 0x00000000U;
889
890 return HAL_OK;
891 }
892
893 /**
894 * @}
895 */
896
897 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
898 * @brief management functions
899 *
900 @verbatim
901 ==============================================================================
902 ##### FMC_SDRAM Control functions #####
903 ==============================================================================
904 [..]
905 This subsection provides a set of functions allowing to control dynamically
906 the FMC SDRAM interface.
907
908 @endverbatim
909 * @{
910 */
911
912 /**
913 * @brief Enables dynamically FMC_SDRAM write protection.
914 * @param Device Pointer to SDRAM device instance
915 * @param Bank SDRAM bank number
916 * @retval HAL status
917 */
FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)918 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
919 {
920 /* Check the parameters */
921 assert_param(IS_FMC_SDRAM_DEVICE(Device));
922 assert_param(IS_FMC_SDRAM_BANK(Bank));
923
924 /* Enable write protection */
925 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
926
927 return HAL_OK;
928 }
929
930 /**
931 * @brief Disables dynamically FMC_SDRAM write protection.
932 * @param hsdram FMC_SDRAM handle
933 * @retval HAL status
934 */
FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)935 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
936 {
937 /* Check the parameters */
938 assert_param(IS_FMC_SDRAM_DEVICE(Device));
939 assert_param(IS_FMC_SDRAM_BANK(Bank));
940
941 /* Disable write protection */
942 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
943
944 return HAL_OK;
945 }
946
947 /**
948 * @brief Send Command to the FMC SDRAM bank
949 * @param Device Pointer to SDRAM device instance
950 * @param Command Pointer to SDRAM command structure
951 * @param Timing Pointer to SDRAM Timing structure
952 * @param Timeout Timeout wait value
953 * @retval HAL state
954 */
FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef * Device,const FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)955 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
956 const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
957 {
958 /* Check the parameters */
959 assert_param(IS_FMC_SDRAM_DEVICE(Device));
960 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
961 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
962 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
963 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
964
965 /* Set command register */
966 MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_DS2 | FMC_SDCMR_DS1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD),
967 ((Command->CommandMode) | (Command->CommandTarget) |
968 (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
969 ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
970 /* Prevent unused argument(s) compilation warning */
971 UNUSED(Timeout);
972 return HAL_OK;
973 }
974
975 /**
976 * @brief Program the SDRAM Memory Refresh rate.
977 * @param Device Pointer to SDRAM device instance
978 * @param RefreshRate The SDRAM refresh rate value.
979 * @retval HAL state
980 */
FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef * Device,uint32_t RefreshRate)981 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
982 {
983 /* Check the parameters */
984 assert_param(IS_FMC_SDRAM_DEVICE(Device));
985 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
986
987 /* Set the refresh rate in command register */
988 MODIFY_REG(Device->SDRTR, FMC_SDRTR_RFSCNT, (RefreshRate << FMC_SDRTR_RFSCNT_Pos));
989
990 return HAL_OK;
991 }
992
993 /**
994 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
995 * @param Device Pointer to SDRAM device instance
996 * @param AutoRefreshNumber Specifies the auto Refresh number.
997 * @retval None
998 */
FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef * Device,uint32_t AutoRefreshNumber)999 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
1000 uint32_t AutoRefreshNumber)
1001 {
1002 /* Check the parameters */
1003 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1004 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1005
1006 /* Set the Auto-refresh number in command register */
1007 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));
1008
1009 return HAL_OK;
1010 }
1011
1012 /**
1013 * @brief Returns the indicated FMC SDRAM bank mode status.
1014 * @param Device Pointer to SDRAM device instance
1015 * @param Bank Defines the FMC SDRAM bank. This parameter can be
1016 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1017 * @retval The FMC SDRAM bank mode status, could be on of the following values:
1018 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1019 * FMC_SDRAM_POWER_DOWN_MODE.
1020 */
FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef * Device,uint32_t Bank)1021 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1022 {
1023 uint32_t tmpreg;
1024
1025 /* Check the parameters */
1026 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1027 assert_param(IS_FMC_SDRAM_BANK(Bank));
1028
1029 /* Get the corresponding bank mode */
1030 if (Bank == FMC_SDRAM_BANK1)
1031 {
1032 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1033 }
1034 else
1035 {
1036 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
1037 }
1038
1039 /* Return the mode status */
1040 return tmpreg;
1041 }
1042
1043 /**
1044 * @}
1045 */
1046
1047 /**
1048 * @}
1049 */
1050
1051
1052 /**
1053 * @}
1054 */
1055
1056 /**
1057 * @}
1058 */
1059
1060 #endif /* HAL_NOR_MODULE_ENABLED */
1061 /**
1062 * @}
1063 */
1064 /**
1065 * @}
1066 */
1067
