281                                      FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)  in FMC_NORSRAM_DeInit()  argument
286   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_DeInit()
289   __FMC_NORSRAM_DISABLE(Device, Bank);  in FMC_NORSRAM_DeInit()
293   if (Bank == FMC_NORSRAM_BANK1)  in FMC_NORSRAM_DeInit()
295     Device->BTCR[Bank] = 0x000030DBU;  in FMC_NORSRAM_DeInit()
300     Device->BTCR[Bank] = 0x000030D2U;  in FMC_NORSRAM_DeInit()
303   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
304   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
318                                           const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NORSRAM_Timing_Init()  argument
332   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Timing_Init()
335   Device->BTCR[Bank + 1U] =  in FMC_NORSRAM_Timing_Init()
369 …                                            const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,  in FMC_NORSRAM_Extended_Timing_Init()  argument
386     assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Extended_Timing_Init()
389 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
398     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FMC_NORSRAM_Extended_Timing_Init()
428 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Enable()  argument
432   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Enable()
435   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Enable()
446 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Disable()  argument
450   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Disable()
453   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Disable()
549 …                                           const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_CommonSpace_Timing_Init()  argument
557   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_CommonSpace_Timing_Init()
560   UNUSED(Bank);  in FMC_NAND_CommonSpace_Timing_Init()
580 …                                           const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_AttributeSpace_Timing_Init()  argument
588   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_AttributeSpace_Timing_Init()
591   UNUSED(Bank);  in FMC_NAND_AttributeSpace_Timing_Init()
608 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_DeInit()  argument
612   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_DeInit()
615   __FMC_NAND_DISABLE(Device, Bank);  in FMC_NAND_DeInit()
619   UNUSED(Bank);  in FMC_NAND_DeInit()
656 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Enable()  argument
660   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Enable()
664   UNUSED(Bank);  in FMC_NAND_ECC_Enable()
678 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Disable()  argument
682   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Disable()
686   UNUSED(Bank);  in FMC_NAND_ECC_Disable()
701 HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FMC_NAND_GetECC()  argument
708   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_GetECC()
714   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)  in FMC_NAND_GetECC()
727   UNUSED(Bank);  in FMC_NAND_GetECC()
845                                         const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)  in FMC_SDRAM_Timing_Init()  argument
856   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_Timing_Init()
877 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_DeInit()  argument
881   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_DeInit()
884   Device->SDCR[Bank] = 0x000002D0U;  in FMC_SDRAM_DeInit()
918 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_WriteProtection_Enable()  argument
922   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_WriteProtection_Enable()
925   SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);  in FMC_SDRAM_WriteProtection_Enable()
935 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_WriteProtection_Disable()  argument
939   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_WriteProtection_Disable()
942   CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);  in FMC_SDRAM_WriteProtection_Disable()
1021 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_GetModeStatus()  argument
1027   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_GetModeStatus()
1030   if (Bank == FMC_SDRAM_BANK1)  in FMC_SDRAM_GetModeStatus()