341                                      FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)  in FMC_NORSRAM_DeInit()  argument
346   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_DeInit()
349   __FMC_NORSRAM_DISABLE(Device, Bank);  in FMC_NORSRAM_DeInit()
353   if (Bank == FMC_NORSRAM_BANK1)  in FMC_NORSRAM_DeInit()
355     Device->BTCR[Bank] = 0x000030DBU;  in FMC_NORSRAM_DeInit()
360     Device->BTCR[Bank] = 0x000030D2U;  in FMC_NORSRAM_DeInit()
363   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
364   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
368   switch (Bank)  in FMC_NORSRAM_DeInit()
400                                           const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NORSRAM_Timing_Init()  argument
416   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Timing_Init()
420   Device->BTCR[Bank + 1U] =  in FMC_NORSRAM_Timing_Init()
430   Device->BTCR[Bank + 1U] =  in FMC_NORSRAM_Timing_Init()
464 …                                            const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,  in FMC_NORSRAM_Extended_Timing_Init()  argument
483     assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Extended_Timing_Init()
487 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
494 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
503     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FMC_NORSRAM_Extended_Timing_Init()
533 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Enable()  argument
537   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Enable()
540   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Enable()
551 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Disable()  argument
555   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Disable()
558   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Disable()
656 …                                           const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_CommonSpace_Timing_Init()  argument
664   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_CommonSpace_Timing_Init()
667   UNUSED(Bank);  in FMC_NAND_CommonSpace_Timing_Init()
687 …                                           const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_AttributeSpace_Timing_Init()  argument
695   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_AttributeSpace_Timing_Init()
698   UNUSED(Bank);  in FMC_NAND_AttributeSpace_Timing_Init()
715 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_DeInit()  argument
719   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_DeInit()
722   __FMC_NAND_DISABLE(Device, Bank);  in FMC_NAND_DeInit()
726   UNUSED(Bank);  in FMC_NAND_DeInit()
763 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Enable()  argument
767   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Enable()
771   UNUSED(Bank);  in FMC_NAND_ECC_Enable()
785 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Disable()  argument
789   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Disable()
793   UNUSED(Bank);  in FMC_NAND_ECC_Disable()
808 HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FMC_NAND_GetECC()  argument
815   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_GetECC()
821   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)  in FMC_NAND_GetECC()
834   UNUSED(Bank);  in FMC_NAND_GetECC()