343                                      FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)  in FSMC_NORSRAM_DeInit()  argument
348   assert_param(IS_FSMC_NORSRAM_BANK(Bank));  in FSMC_NORSRAM_DeInit()
351   __FSMC_NORSRAM_DISABLE(Device, Bank);  in FSMC_NORSRAM_DeInit()
355   if (Bank == FSMC_NORSRAM_BANK1)  in FSMC_NORSRAM_DeInit()
357     Device->BTCR[Bank] = 0x000030DBU;  in FSMC_NORSRAM_DeInit()
362     Device->BTCR[Bank] = 0x000030D2U;  in FSMC_NORSRAM_DeInit()
365   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FSMC_NORSRAM_DeInit()
366   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;  in FSMC_NORSRAM_DeInit()
380                                           FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)  in FSMC_NORSRAM_Timing_Init()  argument
395   assert_param(IS_FSMC_NORSRAM_BANK(Bank));  in FSMC_NORSRAM_Timing_Init()
398 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                     …  in FSMC_NORSRAM_Timing_Init()
432 …                                                 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,  in FSMC_NORSRAM_Extended_Timing_Init()  argument
448     assert_param(IS_FSMC_NORSRAM_BANK(Bank));  in FSMC_NORSRAM_Extended_Timing_Init()
451 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FSMC_NORSRAM_Extended_Timing_Init()
459     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FSMC_NORSRAM_Extended_Timing_Init()
489 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FSMC_NORSRAM_WriteOperation_Enable()  argument
493   assert_param(IS_FSMC_NORSRAM_BANK(Bank));  in FSMC_NORSRAM_WriteOperation_Enable()
496   SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);  in FSMC_NORSRAM_WriteOperation_Enable()
507 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FSMC_NORSRAM_WriteOperation_Disable()  argument
511   assert_param(IS_FSMC_NORSRAM_BANK(Bank));  in FSMC_NORSRAM_WriteOperation_Disable()
514   CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);  in FSMC_NORSRAM_WriteOperation_Disable()
627 …                                                FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FSMC_NAND_CommonSpace_Timing_Init()  argument
635   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_CommonSpace_Timing_Init()
638   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_CommonSpace_Timing_Init()
667 …                                                FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FSMC_NAND_AttributeSpace_Timing_Init()  argument
675   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_AttributeSpace_Timing_Init()
678   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_AttributeSpace_Timing_Init()
704 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_DeInit()  argument
708   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_DeInit()
711   __FSMC_NAND_DISABLE(Device, Bank);  in FSMC_NAND_DeInit()
714   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_DeInit()
761 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_ECC_Enable()  argument
765   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_ECC_Enable()
768   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_ECC_Enable()
787 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_ECC_Disable()  argument
791   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_ECC_Disable()
794   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_ECC_Disable()
814 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FSMC_NAND_GetECC()  argument
821   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_GetECC()
827   while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)  in FSMC_NAND_GetECC()
839   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_GetECC()