1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_fsmc.c
4 * @author MCD Application Team
5 * @brief FSMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Memory Controller (FSMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2016 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### FSMC peripheral features #####
27 ==============================================================================
28 [..] The Flexible memory controller (FSMC) includes following memory controllers:
29 (+) The NOR/PSRAM memory controller
30 (+) The NAND/PC Card memory controller
31
32 [..] The FSMC functional block makes the interface with synchronous and asynchronous static
33 memories and 16-bit PC memory cards. Its main purposes are:
34 (+) to translate AHB transactions into the appropriate external device protocol
35 (+) to meet the access time requirements of the external memory devices
36
37 [..] All external memories share the addresses, data and control signals with the controller.
38 Each external device is accessed by means of a unique Chip Select. The FSMC performs
39 only one access at a time to an external device.
40 The main features of the FSMC controller are the following:
41 (+) Interface with static-memory mapped devices including:
42 (++) Static random access memory (SRAM)
43 (++) Read-only memory (ROM)
44 (++) NOR Flash memory/OneNAND Flash memory
45 (++) PSRAM (4 memory banks)
46 (++) 16-bit PC Card compatible devices
47 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
48 data
49 (+) Independent Chip Select control for each memory bank
50 (+) Independent configuration for each memory bank
51
52 @endverbatim
53 ******************************************************************************
54 */
55
56 /* Includes ------------------------------------------------------------------*/
57 #include "stm32f4xx_hal.h"
58
59 /** @addtogroup STM32F4xx_HAL_Driver
60 * @{
61 */
62 #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) \
63 || defined(HAL_SRAM_MODULE_ENABLED)
64
65 /** @defgroup FSMC_LL FSMC Low Layer
66 * @brief FSMC driver modules
67 * @{
68 */
69
70 /* Private typedef -----------------------------------------------------------*/
71 /* Private define ------------------------------------------------------------*/
72
73 /** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
74 * @{
75 */
76
77 /* ----------------------- FSMC registers bit mask --------------------------- */
78
79 #if defined(FSMC_Bank1)
80 /* --- BCR Register ---*/
81 /* BCR register clear mask */
82
83 /* --- BTR Register ---*/
84 /* BTR register clear mask */
85 #define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD |\
86 FSMC_BTR1_DATAST | FSMC_BTR1_BUSTURN |\
87 FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT |\
88 FSMC_BTR1_ACCMOD))
89
90 /* --- BWTR Register ---*/
91 /* BWTR register clear mask */
92 #define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD |\
93 FSMC_BWTR1_DATAST | FSMC_BWTR1_BUSTURN |\
94 FSMC_BWTR1_ACCMOD))
95 #endif /* FSMC_Bank1 */
96 #if defined(FSMC_Bank2_3)
97
98 #if defined (FSMC_PCR_PWAITEN)
99 /* --- PCR Register ---*/
100 /* PCR register clear mask */
101 #define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCR_PWAITEN | FSMC_PCR_PBKEN | \
102 FSMC_PCR_PTYP | FSMC_PCR_PWID | \
103 FSMC_PCR_ECCEN | FSMC_PCR_TCLR | \
104 FSMC_PCR_TAR | FSMC_PCR_ECCPS))
105 /* --- PMEM Register ---*/
106 /* PMEM register clear mask */
107 #define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEM_MEMSET2 | FSMC_PMEM_MEMWAIT2 |\
108 FSMC_PMEM_MEMHOLD2 | FSMC_PMEM_MEMHIZ2))
109
110 /* --- PATT Register ---*/
111 /* PATT register clear mask */
112 #define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATT_ATTSET2 | FSMC_PATT_ATTWAIT2 |\
113 FSMC_PATT_ATTHOLD2 | FSMC_PATT_ATTHIZ2))
114 #else
115 /* --- PCR Register ---*/
116 /* PCR register clear mask */
117 #define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | \
118 FSMC_PCR2_PTYP | FSMC_PCR2_PWID | \
119 FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
120 FSMC_PCR2_TAR | FSMC_PCR2_ECCPS))
121 /* --- PMEM Register ---*/
122 /* PMEM register clear mask */
123 #define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 |\
124 FSMC_PMEM2_MEMHOLD2 | FSMC_PMEM2_MEMHIZ2))
125
126 /* --- PATT Register ---*/
127 /* PATT register clear mask */
128 #define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 |\
129 FSMC_PATT2_ATTHOLD2 | FSMC_PATT2_ATTHIZ2))
130
131 #endif /* FSMC_PCR_PWAITEN */
132 #endif /* FSMC_Bank2_3 */
133 #if defined(FSMC_Bank4)
134 /* --- PCR Register ---*/
135 /* PCR register clear mask */
136 #define PCR4_CLEAR_MASK ((uint32_t)(FSMC_PCR4_PWAITEN | FSMC_PCR4_PBKEN | \
137 FSMC_PCR4_PTYP | FSMC_PCR4_PWID | \
138 FSMC_PCR4_ECCEN | FSMC_PCR4_TCLR | \
139 FSMC_PCR4_TAR | FSMC_PCR4_ECCPS))
140 /* --- PMEM Register ---*/
141 /* PMEM register clear mask */
142 #define PMEM4_CLEAR_MASK ((uint32_t)(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 |\
143 FSMC_PMEM4_MEMHOLD4 | FSMC_PMEM4_MEMHIZ4))
144
145 /* --- PATT Register ---*/
146 /* PATT register clear mask */
147 #define PATT4_CLEAR_MASK ((uint32_t)(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 |\
148 FSMC_PATT4_ATTHOLD4 | FSMC_PATT4_ATTHIZ4))
149
150 /* --- PIO4 Register ---*/
151 /* PIO4 register clear mask */
152 #define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | \
153 FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
154
155 #endif /* FSMC_Bank4 */
156
157 /**
158 * @}
159 */
160
161 /* Private macro -------------------------------------------------------------*/
162 /* Private variables ---------------------------------------------------------*/
163 /* Private function prototypes -----------------------------------------------*/
164 /* Exported functions --------------------------------------------------------*/
165
166 /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
167 * @{
168 */
169
170 #if defined(FSMC_Bank1)
171
172 /** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions
173 * @brief NORSRAM Controller functions
174 *
175 @verbatim
176 ==============================================================================
177 ##### How to use NORSRAM device driver #####
178 ==============================================================================
179
180 [..]
181 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
182 to run the NORSRAM external devices.
183
184 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
185 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
186 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
187 (+) FSMC NORSRAM bank extended timing configuration using the function
188 FSMC_NORSRAM_Extended_Timing_Init()
189 (+) FSMC NORSRAM bank enable/disable write operation using the functions
190 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
191
192 @endverbatim
193 * @{
194 */
195
196 /** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
197 * @brief Initialization and Configuration functions
198 *
199 @verbatim
200 ==============================================================================
201 ##### Initialization and de_initialization functions #####
202 ==============================================================================
203 [..]
204 This section provides functions allowing to:
205 (+) Initialize and configure the FSMC NORSRAM interface
206 (+) De-initialize the FSMC NORSRAM interface
207 (+) Configure the FSMC clock and associated GPIOs
208
209 @endverbatim
210 * @{
211 */
212
213 /**
214 * @brief Initialize the FSMC_NORSRAM device according to the specified
215 * control parameters in the FSMC_NORSRAM_InitTypeDef
216 * @param Device Pointer to NORSRAM device instance
217 * @param Init Pointer to NORSRAM Initialization structure
218 * @retval HAL status
219 */
FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef * Device,FSMC_NORSRAM_InitTypeDef * Init)220 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
221 FSMC_NORSRAM_InitTypeDef *Init)
222 {
223 uint32_t flashaccess;
224 uint32_t btcr_reg;
225 uint32_t mask;
226
227 /* Check the parameters */
228 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
229 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
230 assert_param(IS_FSMC_MUX(Init->DataAddressMux));
231 assert_param(IS_FSMC_MEMORY(Init->MemoryType));
232 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
233 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
234 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
235 #if defined(FSMC_BCR1_WRAPMOD)
236 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
237 #endif /* FSMC_BCR1_WRAPMOD */
238 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
239 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
240 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
241 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
242 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
243 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
244 #if defined(FSMC_BCR1_CCLKEN)
245 assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock));
246 #endif
247 #if defined(FSMC_BCR1_WFDIS)
248 assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo));
249 #endif /* FSMC_BCR1_WFDIS */
250 assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
251
252 /* Disable NORSRAM Device */
253 __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
254
255 /* Set NORSRAM device control parameters */
256 if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
257 {
258 flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
259 }
260 else
261 {
262 flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
263 }
264
265 btcr_reg = (flashaccess | \
266 Init->DataAddressMux | \
267 Init->MemoryType | \
268 Init->MemoryDataWidth | \
269 Init->BurstAccessMode | \
270 Init->WaitSignalPolarity | \
271 Init->WaitSignalActive | \
272 Init->WriteOperation | \
273 Init->WaitSignal | \
274 Init->ExtendedMode | \
275 Init->AsynchronousWait | \
276 Init->WriteBurst);
277
278 #if defined(FSMC_BCR1_WRAPMOD)
279 btcr_reg |= Init->WrapMode;
280 #endif /* FSMC_BCR1_WRAPMOD */
281 #if defined(FSMC_BCR1_CCLKEN)
282 btcr_reg |= Init->ContinuousClock;
283 #endif /* FSMC_BCR1_CCLKEN */
284 #if defined(FSMC_BCR1_WFDIS)
285 btcr_reg |= Init->WriteFifo;
286 #endif /* FSMC_BCR1_WFDIS */
287 btcr_reg |= Init->PageSize;
288
289 mask = (FSMC_BCR1_MBKEN |
290 FSMC_BCR1_MUXEN |
291 FSMC_BCR1_MTYP |
292 FSMC_BCR1_MWID |
293 FSMC_BCR1_FACCEN |
294 FSMC_BCR1_BURSTEN |
295 FSMC_BCR1_WAITPOL |
296 FSMC_BCR1_WAITCFG |
297 FSMC_BCR1_WREN |
298 FSMC_BCR1_WAITEN |
299 FSMC_BCR1_EXTMOD |
300 FSMC_BCR1_ASYNCWAIT |
301 FSMC_BCR1_CBURSTRW);
302
303 #if defined(FSMC_BCR1_WRAPMOD)
304 mask |= FSMC_BCR1_WRAPMOD;
305 #endif /* FSMC_BCR1_WRAPMOD */
306 #if defined(FSMC_BCR1_CCLKEN)
307 mask |= FSMC_BCR1_CCLKEN;
308 #endif
309 #if defined(FSMC_BCR1_WFDIS)
310 mask |= FSMC_BCR1_WFDIS;
311 #endif /* FSMC_BCR1_WFDIS */
312 mask |= FSMC_BCR1_CPSIZE;
313
314 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
315
316 #if defined(FSMC_BCR1_CCLKEN)
317 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
318 if ((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1))
319 {
320 MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN, Init->ContinuousClock);
321 }
322 #endif
323 #if defined(FSMC_BCR1_WFDIS)
324
325 if (Init->NSBank != FSMC_NORSRAM_BANK1)
326 {
327 /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
328 SET_BIT(Device->BTCR[FSMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
329 }
330 #endif /* FSMC_BCR1_WFDIS */
331
332 return HAL_OK;
333 }
334
335 /**
336 * @brief DeInitialize the FSMC_NORSRAM peripheral
337 * @param Device Pointer to NORSRAM device instance
338 * @param ExDevice Pointer to NORSRAM extended mode device instance
339 * @param Bank NORSRAM bank number
340 * @retval HAL status
341 */
FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef * Device,FSMC_NORSRAM_EXTENDED_TypeDef * ExDevice,uint32_t Bank)342 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
343 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
344 {
345 /* Check the parameters */
346 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
347 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
348 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
349
350 /* Disable the FSMC_NORSRAM device */
351 __FSMC_NORSRAM_DISABLE(Device, Bank);
352
353 /* De-initialize the FSMC_NORSRAM device */
354 /* FSMC_NORSRAM_BANK1 */
355 if (Bank == FSMC_NORSRAM_BANK1)
356 {
357 Device->BTCR[Bank] = 0x000030DBU;
358 }
359 /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
360 else
361 {
362 Device->BTCR[Bank] = 0x000030D2U;
363 }
364
365 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
366 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
367
368 return HAL_OK;
369 }
370
371 /**
372 * @brief Initialize the FSMC_NORSRAM Timing according to the specified
373 * parameters in the FSMC_NORSRAM_TimingTypeDef
374 * @param Device Pointer to NORSRAM device instance
375 * @param Timing Pointer to NORSRAM Timing structure
376 * @param Bank NORSRAM bank number
377 * @retval HAL status
378 */
FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef * Device,FSMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank)379 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
380 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
381 {
382 #if defined(FSMC_BCR1_CCLKEN)
383 uint32_t tmpr;
384 #endif
385
386 /* Check the parameters */
387 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
388 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
389 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
390 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
391 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
392 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
393 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
394 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
395 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
396
397 /* Set FSMC_NORSRAM device timing parameters */
398 MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
399 ((Timing->AddressHoldTime) << FSMC_BTR1_ADDHLD_Pos) |
400 ((Timing->DataSetupTime) << FSMC_BTR1_DATAST_Pos) |
401 ((Timing->BusTurnAroundDuration) << FSMC_BTR1_BUSTURN_Pos) |
402 (((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos) |
403 (((Timing->DataLatency) - 2U) << FSMC_BTR1_DATLAT_Pos) |
404 (Timing->AccessMode)));
405
406 #if defined(FSMC_BCR1_CCLKEN)
407 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
408 if (HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN))
409 {
410 tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FSMC_BTR1_CLKDIV_Pos));
411 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos);
412 MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U], FSMC_BTR1_CLKDIV, tmpr);
413 }
414
415 #endif
416 return HAL_OK;
417 }
418
419 /**
420 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
421 * parameters in the FSMC_NORSRAM_TimingTypeDef
422 * @param Device Pointer to NORSRAM device instance
423 * @param Timing Pointer to NORSRAM Timing structure
424 * @param Bank NORSRAM bank number
425 * @param ExtendedMode FSMC Extended Mode
426 * This parameter can be one of the following values:
427 * @arg FSMC_EXTENDED_MODE_DISABLE
428 * @arg FSMC_EXTENDED_MODE_ENABLE
429 * @retval HAL status
430 */
FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef * Device,FSMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank,uint32_t ExtendedMode)431 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
432 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
433 uint32_t ExtendedMode)
434 {
435 /* Check the parameters */
436 assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
437
438 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
439 if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
440 {
441 /* Check the parameters */
442 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
443 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
444 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
445 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
446 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
447 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
448 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
449
450 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
451 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
452 ((Timing->AddressHoldTime) << FSMC_BWTR1_ADDHLD_Pos) |
453 ((Timing->DataSetupTime) << FSMC_BWTR1_DATAST_Pos) |
454 Timing->AccessMode |
455 ((Timing->BusTurnAroundDuration) << FSMC_BWTR1_BUSTURN_Pos)));
456 }
457 else
458 {
459 Device->BWTR[Bank] = 0x0FFFFFFFU;
460 }
461
462 return HAL_OK;
463 }
464 /**
465 * @}
466 */
467
468 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
469 * @brief management functions
470 *
471 @verbatim
472 ==============================================================================
473 ##### FSMC_NORSRAM Control functions #####
474 ==============================================================================
475 [..]
476 This subsection provides a set of functions allowing to control dynamically
477 the FSMC NORSRAM interface.
478
479 @endverbatim
480 * @{
481 */
482
483 /**
484 * @brief Enables dynamically FSMC_NORSRAM write operation.
485 * @param Device Pointer to NORSRAM device instance
486 * @param Bank NORSRAM bank number
487 * @retval HAL status
488 */
FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef * Device,uint32_t Bank)489 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
490 {
491 /* Check the parameters */
492 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
493 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
494
495 /* Enable write operation */
496 SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
497
498 return HAL_OK;
499 }
500
501 /**
502 * @brief Disables dynamically FSMC_NORSRAM write operation.
503 * @param Device Pointer to NORSRAM device instance
504 * @param Bank NORSRAM bank number
505 * @retval HAL status
506 */
FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef * Device,uint32_t Bank)507 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
508 {
509 /* Check the parameters */
510 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
511 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
512
513 /* Disable write operation */
514 CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
515
516 return HAL_OK;
517 }
518
519 /**
520 * @}
521 */
522
523 /**
524 * @}
525 */
526 #endif /* FSMC_Bank1 */
527
528 #if defined(FSMC_Bank2_3)
529
530 /** @defgroup FSMC_LL_Exported_Functions_NAND FSMC Low Layer NAND Exported Functions
531 * @brief NAND Controller functions
532 *
533 @verbatim
534 ==============================================================================
535 ##### How to use NAND device driver #####
536 ==============================================================================
537 [..]
538 This driver contains a set of APIs to interface with the FSMC NAND banks in order
539 to run the NAND external devices.
540
541 (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
542 (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
543 (+) FSMC NAND bank common space timing configuration using the function
544 FSMC_NAND_CommonSpace_Timing_Init()
545 (+) FSMC NAND bank attribute space timing configuration using the function
546 FSMC_NAND_AttributeSpace_Timing_Init()
547 (+) FSMC NAND bank enable/disable ECC correction feature using the functions
548 FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
549 (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
550
551 @endverbatim
552 * @{
553 */
554
555 /** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
556 * @brief Initialization and Configuration functions
557 *
558 @verbatim
559 ==============================================================================
560 ##### Initialization and de_initialization functions #####
561 ==============================================================================
562 [..]
563 This section provides functions allowing to:
564 (+) Initialize and configure the FSMC NAND interface
565 (+) De-initialize the FSMC NAND interface
566 (+) Configure the FSMC clock and associated GPIOs
567
568 @endverbatim
569 * @{
570 */
571
572 /**
573 * @brief Initializes the FSMC_NAND device according to the specified
574 * control parameters in the FSMC_NAND_HandleTypeDef
575 * @param Device Pointer to NAND device instance
576 * @param Init Pointer to NAND Initialization structure
577 * @retval HAL status
578 */
FSMC_NAND_Init(FSMC_NAND_TypeDef * Device,FSMC_NAND_InitTypeDef * Init)579 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
580 {
581 /* Check the parameters */
582 assert_param(IS_FSMC_NAND_DEVICE(Device));
583 assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
584 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
585 assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
586 assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
587 assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
588 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
589 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
590
591 /* Set NAND device control parameters */
592 if (Init->NandBank == FSMC_NAND_BANK2)
593 {
594 /* NAND bank 2 registers configuration */
595 MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
596 FSMC_PCR_MEMORY_TYPE_NAND |
597 Init->MemoryDataWidth |
598 Init->EccComputation |
599 Init->ECCPageSize |
600 ((Init->TCLRSetupTime) << FSMC_PCR2_TCLR_Pos) |
601 ((Init->TARSetupTime) << FSMC_PCR2_TAR_Pos)));
602 }
603 else
604 {
605 /* NAND bank 3 registers configuration */
606 MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
607 FSMC_PCR_MEMORY_TYPE_NAND |
608 Init->MemoryDataWidth |
609 Init->EccComputation |
610 Init->ECCPageSize |
611 ((Init->TCLRSetupTime) << FSMC_PCR2_TCLR_Pos) |
612 ((Init->TARSetupTime) << FSMC_PCR2_TAR_Pos)));
613 }
614
615 return HAL_OK;
616 }
617
618 /**
619 * @brief Initializes the FSMC_NAND Common space Timing according to the specified
620 * parameters in the FSMC_NAND_PCC_TimingTypeDef
621 * @param Device Pointer to NAND device instance
622 * @param Timing Pointer to NAND timing structure
623 * @param Bank NAND bank number
624 * @retval HAL status
625 */
FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef * Device,FSMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)626 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
627 FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
628 {
629 /* Check the parameters */
630 assert_param(IS_FSMC_NAND_DEVICE(Device));
631 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
632 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
633 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
634 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
635 assert_param(IS_FSMC_NAND_BANK(Bank));
636
637 /* Set FSMC_NAND device timing parameters */
638 if (Bank == FSMC_NAND_BANK2)
639 {
640 /* NAND bank 2 registers configuration */
641 MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime |
642 ((Timing->WaitSetupTime) << FSMC_PMEM2_MEMWAIT2_Pos) |
643 ((Timing->HoldSetupTime) << FSMC_PMEM2_MEMHOLD2_Pos) |
644 ((Timing->HiZSetupTime) << FSMC_PMEM2_MEMHIZ2_Pos)));
645 }
646 else
647 {
648 /* NAND bank 3 registers configuration */
649 MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime |
650 ((Timing->WaitSetupTime) << FSMC_PMEM2_MEMWAIT2_Pos) |
651 ((Timing->HoldSetupTime) << FSMC_PMEM2_MEMHOLD2_Pos) |
652 ((Timing->HiZSetupTime) << FSMC_PMEM2_MEMHIZ2_Pos)));
653 }
654
655 return HAL_OK;
656 }
657
658 /**
659 * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
660 * parameters in the FSMC_NAND_PCC_TimingTypeDef
661 * @param Device Pointer to NAND device instance
662 * @param Timing Pointer to NAND timing structure
663 * @param Bank NAND bank number
664 * @retval HAL status
665 */
FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef * Device,FSMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)666 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
667 FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
668 {
669 /* Check the parameters */
670 assert_param(IS_FSMC_NAND_DEVICE(Device));
671 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
672 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
673 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
674 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
675 assert_param(IS_FSMC_NAND_BANK(Bank));
676
677 /* Set FSMC_NAND device timing parameters */
678 if (Bank == FSMC_NAND_BANK2)
679 {
680 /* NAND bank 2 registers configuration */
681 MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime |
682 ((Timing->WaitSetupTime) << FSMC_PATT2_ATTWAIT2_Pos) |
683 ((Timing->HoldSetupTime) << FSMC_PATT2_ATTHOLD2_Pos) |
684 ((Timing->HiZSetupTime) << FSMC_PATT2_ATTHIZ2_Pos)));
685 }
686 else
687 {
688 /* NAND bank 3 registers configuration */
689 MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime |
690 ((Timing->WaitSetupTime) << FSMC_PATT2_ATTWAIT2_Pos) |
691 ((Timing->HoldSetupTime) << FSMC_PATT2_ATTHOLD2_Pos) |
692 ((Timing->HiZSetupTime) << FSMC_PATT2_ATTHIZ2_Pos)));
693 }
694
695 return HAL_OK;
696 }
697
698 /**
699 * @brief DeInitializes the FSMC_NAND device
700 * @param Device Pointer to NAND device instance
701 * @param Bank NAND bank number
702 * @retval HAL status
703 */
FSMC_NAND_DeInit(FSMC_NAND_TypeDef * Device,uint32_t Bank)704 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
705 {
706 /* Check the parameters */
707 assert_param(IS_FSMC_NAND_DEVICE(Device));
708 assert_param(IS_FSMC_NAND_BANK(Bank));
709
710 /* Disable the NAND Bank */
711 __FSMC_NAND_DISABLE(Device, Bank);
712
713 /* De-initialize the NAND Bank */
714 if (Bank == FSMC_NAND_BANK2)
715 {
716 /* Set the FSMC_NAND_BANK2 registers to their reset values */
717 WRITE_REG(Device->PCR2, 0x00000018U);
718 WRITE_REG(Device->SR2, 0x00000040U);
719 WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
720 WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
721 }
722 /* FSMC_Bank3_NAND */
723 else
724 {
725 /* Set the FSMC_NAND_BANK3 registers to their reset values */
726 WRITE_REG(Device->PCR3, 0x00000018U);
727 WRITE_REG(Device->SR3, 0x00000040U);
728 WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
729 WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
730 }
731
732 return HAL_OK;
733 }
734
735 /**
736 * @}
737 */
738
739 /** @defgroup HAL_FSMC_NAND_Group2 Peripheral Control functions
740 * @brief management functions
741 *
742 @verbatim
743 ==============================================================================
744 ##### FSMC_NAND Control functions #####
745 ==============================================================================
746 [..]
747 This subsection provides a set of functions allowing to control dynamically
748 the FSMC NAND interface.
749
750 @endverbatim
751 * @{
752 */
753
754
755 /**
756 * @brief Enables dynamically FSMC_NAND ECC feature.
757 * @param Device Pointer to NAND device instance
758 * @param Bank NAND bank number
759 * @retval HAL status
760 */
FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef * Device,uint32_t Bank)761 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
762 {
763 /* Check the parameters */
764 assert_param(IS_FSMC_NAND_DEVICE(Device));
765 assert_param(IS_FSMC_NAND_BANK(Bank));
766
767 /* Enable ECC feature */
768 if (Bank == FSMC_NAND_BANK2)
769 {
770 SET_BIT(Device->PCR2, FSMC_PCR2_ECCEN);
771 }
772 else
773 {
774 SET_BIT(Device->PCR3, FSMC_PCR2_ECCEN);
775 }
776
777 return HAL_OK;
778 }
779
780
781 /**
782 * @brief Disables dynamically FSMC_NAND ECC feature.
783 * @param Device Pointer to NAND device instance
784 * @param Bank NAND bank number
785 * @retval HAL status
786 */
FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef * Device,uint32_t Bank)787 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
788 {
789 /* Check the parameters */
790 assert_param(IS_FSMC_NAND_DEVICE(Device));
791 assert_param(IS_FSMC_NAND_BANK(Bank));
792
793 /* Disable ECC feature */
794 if (Bank == FSMC_NAND_BANK2)
795 {
796 CLEAR_BIT(Device->PCR2, FSMC_PCR2_ECCEN);
797 }
798 else
799 {
800 CLEAR_BIT(Device->PCR3, FSMC_PCR2_ECCEN);
801 }
802
803 return HAL_OK;
804 }
805
806 /**
807 * @brief Disables dynamically FSMC_NAND ECC feature.
808 * @param Device Pointer to NAND device instance
809 * @param ECCval Pointer to ECC value
810 * @param Bank NAND bank number
811 * @param Timeout Timeout wait value
812 * @retval HAL status
813 */
FSMC_NAND_GetECC(FSMC_NAND_TypeDef * Device,uint32_t * ECCval,uint32_t Bank,uint32_t Timeout)814 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
815 uint32_t Timeout)
816 {
817 uint32_t tickstart;
818
819 /* Check the parameters */
820 assert_param(IS_FSMC_NAND_DEVICE(Device));
821 assert_param(IS_FSMC_NAND_BANK(Bank));
822
823 /* Get tick */
824 tickstart = HAL_GetTick();
825
826 /* Wait until FIFO is empty */
827 while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
828 {
829 /* Check for the Timeout */
830 if (Timeout != HAL_MAX_DELAY)
831 {
832 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
833 {
834 return HAL_TIMEOUT;
835 }
836 }
837 }
838
839 if (Bank == FSMC_NAND_BANK2)
840 {
841 /* Get the ECCR2 register value */
842 *ECCval = (uint32_t)Device->ECCR2;
843 }
844 else
845 {
846 /* Get the ECCR3 register value */
847 *ECCval = (uint32_t)Device->ECCR3;
848 }
849
850 return HAL_OK;
851 }
852
853 /**
854 * @}
855 */
856 #endif /* FSMC_Bank2_3 */
857
858 #if defined(FSMC_Bank4)
859
860 /** @addtogroup FSMC_LL_PCCARD
861 * @brief PCCARD Controller functions
862 *
863 @verbatim
864 ==============================================================================
865 ##### How to use PCCARD device driver #####
866 ==============================================================================
867 [..]
868 This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
869 to run the PCCARD/compact flash external devices.
870
871 (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
872 (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
873 (+) FSMC PCCARD bank common space timing configuration using the function
874 FSMC_PCCARD_CommonSpace_Timing_Init()
875 (+) FSMC PCCARD bank attribute space timing configuration using the function
876 FSMC_PCCARD_AttributeSpace_Timing_Init()
877 (+) FSMC PCCARD bank IO space timing configuration using the function
878 FSMC_PCCARD_IOSpace_Timing_Init()
879 @endverbatim
880 * @{
881 */
882
883 /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
884 * @brief Initialization and Configuration functions
885 *
886 @verbatim
887 ==============================================================================
888 ##### Initialization and de_initialization functions #####
889 ==============================================================================
890 [..]
891 This section provides functions allowing to:
892 (+) Initialize and configure the FSMC PCCARD interface
893 (+) De-initialize the FSMC PCCARD interface
894 (+) Configure the FSMC clock and associated GPIOs
895
896 @endverbatim
897 * @{
898 */
899
900 /**
901 * @brief Initializes the FSMC_PCCARD device according to the specified
902 * control parameters in the FSMC_PCCARD_HandleTypeDef
903 * @param Device Pointer to PCCARD device instance
904 * @param Init Pointer to PCCARD Initialization structure
905 * @retval HAL status
906 */
FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef * Device,FSMC_PCCARD_InitTypeDef * Init)907 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
908 {
909 /* Check the parameters */
910 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
911 #if defined(FSMC_Bank2_3)
912 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
913 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
914 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
915 #endif /* FSMC_Bank2_3 */
916
917 /* Set FSMC_PCCARD device control parameters */
918 MODIFY_REG(Device->PCR4,
919 (FSMC_PCR4_PTYP |
920 FSMC_PCR4_PWAITEN |
921 FSMC_PCR4_PWID |
922 FSMC_PCR4_TCLR |
923 FSMC_PCR4_TAR),
924 (FSMC_PCR_MEMORY_TYPE_PCCARD |
925 Init->Waitfeature |
926 FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |
927 (Init->TCLRSetupTime << FSMC_PCR4_TCLR_Pos) |
928 (Init->TARSetupTime << FSMC_PCR4_TAR_Pos)));
929
930 return HAL_OK;
931 }
932
933 /**
934 * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
935 * parameters in the FSMC_NAND_PCC_TimingTypeDef
936 * @param Device Pointer to PCCARD device instance
937 * @param Timing Pointer to PCCARD timing structure
938 * @retval HAL status
939 */
FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef * Device,FSMC_NAND_PCC_TimingTypeDef * Timing)940 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
941 FSMC_NAND_PCC_TimingTypeDef *Timing)
942 {
943 /* Check the parameters */
944 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
945 #if defined(FSMC_Bank2_3)
946 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
947 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
948 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
949 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
950 #endif /* FSMC_Bank2_3 */
951
952 /* Set PCCARD timing parameters */
953 MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK,
954 (Timing->SetupTime |
955 ((Timing->WaitSetupTime) << FSMC_PMEM4_MEMWAIT4_Pos) |
956 ((Timing->HoldSetupTime) << FSMC_PMEM4_MEMHOLD4_Pos) |
957 ((Timing->HiZSetupTime) << FSMC_PMEM4_MEMHIZ4_Pos)));
958
959 return HAL_OK;
960 }
961
962 /**
963 * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
964 * parameters in the FSMC_NAND_PCC_TimingTypeDef
965 * @param Device Pointer to PCCARD device instance
966 * @param Timing Pointer to PCCARD timing structure
967 * @retval HAL status
968 */
FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef * Device,FSMC_NAND_PCC_TimingTypeDef * Timing)969 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
970 FSMC_NAND_PCC_TimingTypeDef *Timing)
971 {
972 /* Check the parameters */
973 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
974 #if defined(FSMC_Bank2_3)
975 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
976 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
977 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
978 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
979 #endif /* FSMC_Bank2_3 */
980
981 /* Set PCCARD timing parameters */
982 MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK,
983 (Timing->SetupTime |
984 ((Timing->WaitSetupTime) << FSMC_PATT4_ATTWAIT4_Pos) |
985 ((Timing->HoldSetupTime) << FSMC_PATT4_ATTHOLD4_Pos) |
986 ((Timing->HiZSetupTime) << FSMC_PATT4_ATTHIZ4_Pos)));
987
988 return HAL_OK;
989 }
990
991 /**
992 * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
993 * parameters in the FSMC_NAND_PCC_TimingTypeDef
994 * @param Device Pointer to PCCARD device instance
995 * @param Timing Pointer to PCCARD timing structure
996 * @retval HAL status
997 */
FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef * Device,FSMC_NAND_PCC_TimingTypeDef * Timing)998 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
999 FSMC_NAND_PCC_TimingTypeDef *Timing)
1000 {
1001 /* Check the parameters */
1002 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
1003 #if defined(FSMC_Bank2_3)
1004 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
1005 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
1006 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
1007 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
1008 #endif /* FSMC_Bank2_3 */
1009
1010 /* Set FSMC_PCCARD device timing parameters */
1011 MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
1012 (Timing->SetupTime |
1013 (Timing->WaitSetupTime << FSMC_PIO4_IOWAIT4_Pos) |
1014 (Timing->HoldSetupTime << FSMC_PIO4_IOHOLD4_Pos) |
1015 (Timing->HiZSetupTime << FSMC_PIO4_IOHIZ4_Pos)));
1016
1017 return HAL_OK;
1018 }
1019
1020 /**
1021 * @brief DeInitializes the FSMC_PCCARD device
1022 * @param Device Pointer to PCCARD device instance
1023 * @retval HAL status
1024 */
FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef * Device)1025 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
1026 {
1027 /* Check the parameters */
1028 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
1029
1030 /* Disable the FSMC_PCCARD device */
1031 __FSMC_PCCARD_DISABLE(Device);
1032
1033 /* De-initialize the FSMC_PCCARD device */
1034 Device->PCR4 = 0x00000018U;
1035 Device->SR4 = 0x00000040U;
1036 Device->PMEM4 = 0xFCFCFCFCU;
1037 Device->PATT4 = 0xFCFCFCFCU;
1038 Device->PIO4 = 0xFCFCFCFCU;
1039
1040 return HAL_OK;
1041 }
1042
1043 /**
1044 * @}
1045 */
1046 #endif /* FSMC_Bank4 */
1047
1048
1049 /**
1050 * @}
1051 */
1052
1053 /**
1054 * @}
1055 */
1056
1057 #endif /* HAL_NOR_MODULE_ENABLED */
1058 /**
1059 * @}
1060 */
1061 /**
1062 * @}
1063 */
1064
