288                                      FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)  in FMC_NORSRAM_DeInit()  argument
293   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_DeInit()
296   __FMC_NORSRAM_DISABLE(Device, Bank);  in FMC_NORSRAM_DeInit()
300   if (Bank == FMC_NORSRAM_BANK1)  in FMC_NORSRAM_DeInit()
302     Device->BTCR[Bank] = 0x000030DBU;  in FMC_NORSRAM_DeInit()
307     Device->BTCR[Bank] = 0x000030D2U;  in FMC_NORSRAM_DeInit()
310   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
311   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
325                                           const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NORSRAM_Timing_Init()  argument
338   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Timing_Init()
341   Device->BTCR[Bank + 1U] =  in FMC_NORSRAM_Timing_Init()
374 …                                            const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,  in FMC_NORSRAM_Extended_Timing_Init()  argument
390     assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Extended_Timing_Init()
393 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
401     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FMC_NORSRAM_Extended_Timing_Init()
431 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Enable()  argument
435   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Enable()
438   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Enable()
449 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Disable()  argument
453   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Disable()
456   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Disable()
552 …                                           const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_CommonSpace_Timing_Init()  argument
560   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_CommonSpace_Timing_Init()
563   UNUSED(Bank);  in FMC_NAND_CommonSpace_Timing_Init()
583 …                                           const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_AttributeSpace_Timing_Init()  argument
591   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_AttributeSpace_Timing_Init()
594   UNUSED(Bank);  in FMC_NAND_AttributeSpace_Timing_Init()
611 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_DeInit()  argument
615   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_DeInit()
618   __FMC_NAND_DISABLE(Device, Bank);  in FMC_NAND_DeInit()
622   UNUSED(Bank);  in FMC_NAND_DeInit()
659 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Enable()  argument
663   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Enable()
667   UNUSED(Bank);  in FMC_NAND_ECC_Enable()
681 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Disable()  argument
685   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Disable()
689   UNUSED(Bank);  in FMC_NAND_ECC_Disable()
704 HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FMC_NAND_GetECC()  argument
711   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_GetECC()
717   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)  in FMC_NAND_GetECC()
730   UNUSED(Bank);  in FMC_NAND_GetECC()
852                                         const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)  in FMC_SDRAM_Timing_Init()  argument
863   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_Timing_Init()
866   if (Bank == FMC_SDRAM_BANK1)  in FMC_SDRAM_Timing_Init()
903 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_DeInit()  argument
907   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_DeInit()
910   Device->SDCR[Bank] = 0x000002D0U;  in FMC_SDRAM_DeInit()
911   Device->SDTR[Bank] = 0x0FFFFFFFU;  in FMC_SDRAM_DeInit()
944 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_WriteProtection_Enable()  argument
948   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_WriteProtection_Enable()
951   SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);  in FMC_SDRAM_WriteProtection_Enable()
961 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_WriteProtection_Disable()  argument
965   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_WriteProtection_Disable()
968   CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);  in FMC_SDRAM_WriteProtection_Disable()
1047 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_GetModeStatus()  argument
1053   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_GetModeStatus()
1056   if (Bank == FMC_SDRAM_BANK1)  in FMC_SDRAM_GetModeStatus()