305                                      FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)  in FMC_NORSRAM_DeInit()  argument
310   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_DeInit()
313   __FMC_NORSRAM_DISABLE(Device, Bank);  in FMC_NORSRAM_DeInit()
317   if (Bank == FMC_NORSRAM_BANK1)  in FMC_NORSRAM_DeInit()
319     Device->BTCR[Bank] = 0x000030DBU;  in FMC_NORSRAM_DeInit()
324     Device->BTCR[Bank] = 0x000030D2U;  in FMC_NORSRAM_DeInit()
327   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
328   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
331   switch (Bank)  in FMC_NORSRAM_DeInit()
362                                           FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NORSRAM_Timing_Init()  argument
376   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Timing_Init()
379   Device->BTCR[Bank + 1U] =  in FMC_NORSRAM_Timing_Init()
413                                                    FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,  in FMC_NORSRAM_Extended_Timing_Init()  argument
430     assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Extended_Timing_Init()
433 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
442     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FMC_NORSRAM_Extended_Timing_Init()
472 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Enable()  argument
476   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Enable()
479   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Enable()
490 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Disable()  argument
494   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Disable()
497   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Disable()
593 …                                                 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_CommonSpace_Timing_Init()  argument
601   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_CommonSpace_Timing_Init()
604   UNUSED(Bank);  in FMC_NAND_CommonSpace_Timing_Init()
624 …                                                 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_AttributeSpace_Timing_Init()  argument
632   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_AttributeSpace_Timing_Init()
635   UNUSED(Bank);  in FMC_NAND_AttributeSpace_Timing_Init()
652 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_DeInit()  argument
656   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_DeInit()
659   __FMC_NAND_DISABLE(Device, Bank);  in FMC_NAND_DeInit()
663   UNUSED(Bank);  in FMC_NAND_DeInit()
700 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Enable()  argument
704   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Enable()
708   UNUSED(Bank);  in FMC_NAND_ECC_Enable()
722 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Disable()  argument
726   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Disable()
730   UNUSED(Bank);  in FMC_NAND_ECC_Disable()
745 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FMC_NAND_GetECC()  argument
752   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_GetECC()
758   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)  in FMC_NAND_GetECC()
771   UNUSED(Bank);  in FMC_NAND_GetECC()