1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_flash_ex.c
4 * @author MCD Application Team
5 * @brief Extended FLASH HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the FLASH extension peripheral:
8 * + Extended programming operations functions
9 *
10 ******************************************************************************
11 * @attention
12 *
13 * Copyright (c) 2023 STMicroelectronics.
14 * All rights reserved.
15 *
16 * This software is licensed under terms that can be found in the LICENSE file
17 * in the root directory of this software component.
18 * If no LICENSE file comes with this software, it is provided AS-IS.
19 *
20 ******************************************************************************
21 @verbatim
22 ==============================================================================
23 ##### Flash Extension features #####
24 ==============================================================================
25
26 [..] Comparing to other previous devices, the FLASH interface for STM32H5xx
27 devices contains the following additional features
28
29 (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
30 capability (RWW)
31 (+) Dual bank memory organization
32 (+) Product State protection
33 (+) Write protection
34 (+) Secure access only protection
35 (+) Bank / register swapping (when Dual-Bank)
36 (+) Watermark-based secure protection
37 (+) Block-based secure protection
38 (+) Block-based privilege protection
39 (+) Hide Protection areas
40
41 ##### How to use this driver #####
42 ==============================================================================
43 [..] This driver provides functions to configure and program the FLASH memory
44 of all STM32H5xx devices. It includes
45 (#) FLASH Memory Erase functions:
46 (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
47 HAL_FLASH_Lock() functions
48 (++) Erase function: Sector erase, bank erase and dual-bank mass erase
49 (++) There are two modes of erase :
50 (+++) Polling Mode using HAL_FLASHEx_Erase()
51 (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
52
53 (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to:
54 (++) Configure the write protection per bank
55 (++) Set the Product State
56 (++) Program the user Option Bytes
57 (++) Configure the watermark security for each area
58 (++) Configure the Hide protection areas
59 (++) Configure the Boot addresses
60
61 (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to:
62 (++) Get the value of a write protection area
63 (++) Get the Product State
64 (++) Get the value of the user Option Bytes
65 (++) Get the configuration of watermark security areas
66 (++) Get the configuration of Hide protection areas
67 (++) Get the value of a boot address
68
69 (#) Block-based secure / privilege area configuration function: Use HAL_FLASHEx_ConfigBBAttributes()
70 (++) Bit-field allowing to secure or un-secure each sector
71 (++) Bit-field allowing to privilege or un-privilege each sector
72
73 (#) Get the block-based secure / privilege area configuration function: Use HAL_FLASHEx_GetConfigBBAttributes()
74 (++) Return the configuration of the block-based security and privilege for all the sectors
75
76 (#) Privilege mode configuration function: Use HAL_FLASHEx_ConfigPrivMode()
77 (++) FLASH register can be protected against non-privilege accesses
78
79 (#) Get the privilege mode configuration function: Use HAL_FLASHEx_GetPrivMode()
80 (++) Return if the FLASH registers are protected against non-privilege accesses
81
82
83 @endverbatim
84 */
85
86 /* Includes ------------------------------------------------------------------*/
87 #include "stm32h5xx_hal.h"
88
89 /** @addtogroup STM32H5xx_HAL_Driver
90 * @{
91 */
92
93 /** @defgroup FLASHEx FLASHEx
94 * @brief FLASH HAL Extension module driver
95 * @{
96 */
97
98 #ifdef HAL_FLASH_MODULE_ENABLED
99
100 /* Private typedef -----------------------------------------------------------*/
101 /* Private define ------------------------------------------------------------*/
102 /* Private macro -------------------------------------------------------------*/
103 /* Private variables ---------------------------------------------------------*/
104 /* Private function prototypes -----------------------------------------------*/
105 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
106 * @{
107 */
108 static void FLASH_MassErase(uint32_t Banks);
109 #if defined (FLASH_SR_OBKERR)
110 static void FLASH_OBKErase(void);
111 #endif /* FLASH_SR_OBKERR */
112 static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
113 static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank);
114 static void FLASH_OB_GetWRP(uint32_t Bank, uint32_t *WRPState, uint32_t *WRPSector);
115 static void FLASH_OB_ProdStateConfig(uint32_t ProdStateConfig);
116 static uint32_t FLASH_OB_GetProdState(void);
117 static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig1, uint32_t UserConfig2);
118 static void FLASH_OB_GetUser(uint32_t *UserConfig1, uint32_t *UserConfig2);
119 static void FLASH_OB_BootAddrConfig(uint32_t BootOption, uint32_t BootAddress);
120 static void FLASH_OB_BootLockConfig(uint32_t BootLockOption, uint32_t BootLockConfig);
121 static void FLASH_OB_GetBootConfig(uint32_t BootOption, uint32_t *BootAddress, uint32_t *BootLockConfig);
122 static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block);
123 static uint32_t FLASH_OB_OTP_GetLock(void);
124 static void FLASH_OB_HDPConfig(uint32_t Banks, uint32_t HDPStartSector, uint32_t HDPEndSector);
125 static void FLASH_OB_GetHDP(uint32_t Bank, uint32_t *HDPStartSector, uint32_t *HDPEndSector);
126 #if defined(FLASH_EDATAR_EDATA_EN)
127 static void FLASH_OB_EDATAConfig(uint32_t Banks, uint32_t EDATASize);
128 static void FLASH_OB_GetEDATA(uint32_t Bank, uint32_t *EDATASize);
129 #endif /* FLASH_EDATAR_EDATA_EN */
130 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
131 static void FLASH_OB_WMSECConfig(uint32_t Banks, uint32_t WMSecStartSector, uint32_t WMSecEndSector);
132 static void FLASH_OB_GetWMSEC(uint32_t Bank, uint32_t *WMSecStartSector, uint32_t *WMSecEndSector);
133 #endif /* __ARM_FEATURE_CMSE */
134 /**
135 * @}
136 */
137
138 /* Exported functions ---------------------------------------------------------*/
139 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
140 * @{
141 */
142
143 /** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Extended IO operation functions
144 * @brief FLASHEx Extended IO operation functions
145 *
146 @verbatim
147 ===============================================================================
148 ##### Extended programming operation functions #####
149 ===============================================================================
150 [..]
151 This subsection provides a set of functions allowing to manage the Extended FLASH
152 programming operations Operations.
153
154 @endverbatim
155 * @{
156 */
157 /**
158 * @brief Perform a mass erase or erase the specified FLASH memory sectors
159 * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
160 * contains the configuration information for the erasing.
161 *
162 * @param[out] SectorError pointer to variable that contains the configuration
163 * information on faulty sector in case of error (0xFFFFFFFF means that all
164 * the sectors have been correctly erased).
165 *
166 * @retval HAL Status
167 */
HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef * pEraseInit,uint32_t * SectorError)168 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
169 {
170 HAL_StatusTypeDef status;
171 uint32_t sector_index;
172 __IO uint32_t *reg_cr;
173
174 /* Check the parameters */
175 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
176
177 /* Process Locked */
178 __HAL_LOCK(&pFlash);
179
180 /* Reset error code */
181 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
182
183 /* Wait for last operation to be completed */
184 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
185
186 if (status == HAL_OK)
187 {
188 /* Current operation type */
189 pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
190
191 /* Access to SECCR or NSCR depends on operation type */
192 #if defined (FLASH_OPTSR2_TZEN)
193 reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
194 #else
195 reg_cr = &(FLASH_NS->NSCR);
196 #endif /* FLASH_OPTSR2_TZEN */
197
198 if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE)
199 {
200 /* Mass erase to be done */
201 FLASH_MassErase(pEraseInit->Banks);
202
203 /* Wait for last operation to be completed */
204 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
205 }
206 #if defined (FLASH_SR_OBKERR)
207 else if (pEraseInit->TypeErase == FLASH_TYPEERASE_OBK_ALT)
208 {
209 /* OBK erase to be done */
210 FLASH_OBKErase();
211
212 /* Wait for last operation to be completed */
213 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
214 }
215 #endif /* FLASH_SR_OBKERR */
216 else
217 {
218 /* Initialization of SectorError variable */
219 *SectorError = 0xFFFFFFFFU;
220
221 /* Erase by sector by sector to be done*/
222 for (sector_index = pEraseInit->Sector; sector_index < (pEraseInit->NbSectors + pEraseInit->Sector); \
223 sector_index++)
224 {
225 FLASH_Erase_Sector(sector_index, pEraseInit->Banks);
226
227 /* Wait for last operation to be completed */
228 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
229
230 if (status != HAL_OK)
231 {
232 /* In case of error, stop erase procedure and return the faulty sector */
233 *SectorError = sector_index;
234 break;
235 }
236 }
237 }
238
239 /* If the erase operation is completed, disable the associated bits */
240 CLEAR_BIT((*reg_cr), (pEraseInit->TypeErase) & (~(FLASH_NON_SECURE_MASK)));
241 }
242
243 /* Process Unlocked */
244 __HAL_UNLOCK(&pFlash);
245
246 return status;
247 }
248
249 /**
250 * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
251 * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
252 * contains the configuration information for the erasing.
253 *
254 * @retval HAL Status
255 */
HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef * pEraseInit)256 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
257 {
258 HAL_StatusTypeDef status;
259 __IO uint32_t *reg_cr;
260
261 /* Check the parameters */
262 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
263
264 /* Reset error code */
265 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
266
267 /* Wait for last operation to be completed */
268 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
269
270 if (status != HAL_OK)
271 {
272 return status;
273 }
274 else
275 {
276 /* Set internal variables used by the IRQ handler */
277 pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
278 pFlash.Bank = pEraseInit->Banks;
279
280 /* Access to SECCR or NSCR depends on operation type */
281 #if defined (FLASH_OPTSR2_TZEN)
282 reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
283 #else
284 reg_cr = &(FLASH_NS->NSCR);
285 #endif /* FLASH_OPTSR2_TZEN */
286
287 /* Enable End of Operation and Error interrupts */
288 #if defined (FLASH_SR_OBKERR)
289 (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | \
290 FLASH_IT_STRBERR | FLASH_IT_INCERR | FLASH_IT_OBKERR | \
291 FLASH_IT_OBKWERR);
292 #else
293 (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | \
294 FLASH_IT_STRBERR | FLASH_IT_INCERR);
295 #endif /* FLASH_SR_OBKERR */
296
297 if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE)
298 {
299 /* Mass erase to be done */
300 FLASH_MassErase(pEraseInit->Banks);
301 }
302 #if defined (FLASH_SR_OBKERR)
303 else if (pEraseInit->TypeErase == FLASH_TYPEERASE_OBK_ALT)
304 {
305 /* OBK erase to be done */
306 FLASH_OBKErase();
307 }
308 #endif /* FLASH_SR_OBKERR */
309 else
310 {
311 /* Erase by sector to be done */
312 pFlash.NbSectorsToErase = pEraseInit->NbSectors;
313 pFlash.Sector = pEraseInit->Sector;
314
315 /* Erase first sector and wait for IT */
316 FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->Banks);
317 }
318 }
319
320 return status;
321 }
322
323 /**
324 * @brief Program option bytes
325 * @param pOBInit pointer to an FLASH_OBInitStruct structure that
326 * contains the configuration information for the programming.
327 *
328 * @note To configure any option bytes, the option lock bit OPTLOCK must be
329 * cleared with the call of HAL_FLASH_OB_Unlock() function.
330 * @note New option bytes configuration will be taken into account in two cases:
331 * - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
332 * - after a power-on reset (BOR reset or exit from Standby/Shutdown modes)
333 * @retval HAL Status
334 */
HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef * pOBInit)335 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
336 {
337 HAL_StatusTypeDef status;
338
339 /* Check the parameters */
340 assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
341
342 /* Process Locked */
343 __HAL_LOCK(&pFlash);
344
345 /* Reset Error Code */
346 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
347
348 /* Current operation type */
349 pFlash.ProcedureOnGoing = FLASH_TYPEPROGRAM_OB;
350
351 /* Wait for last operation to be completed */
352 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
353
354 if (status == HAL_OK)
355 {
356 /*Write protection configuration*/
357 if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U)
358 {
359 assert_param(IS_WRPSTATE(pOBInit->WRPState));
360
361 if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
362 {
363 /* Enable write protection on the selected sectors */
364 FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks);
365 }
366 else
367 {
368 /* Disable write protection on the selected sectors */
369 FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
370 }
371 }
372
373 /* Product State configuration */
374 if ((pOBInit->OptionType & OPTIONBYTE_PROD_STATE) != 0U)
375 {
376 /* Configure the product state */
377 FLASH_OB_ProdStateConfig(pOBInit->ProductState);
378 }
379
380 /* User Configuration */
381 if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
382 {
383 /* Configure the user option bytes */
384 FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig, pOBInit->USERConfig2);
385 }
386
387 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
388 /* Watermark secure configuration */
389 if ((pOBInit->OptionType & OPTIONBYTE_WMSEC) != 0U)
390 {
391 /* Configure the watermark-based secure area */
392 FLASH_OB_WMSECConfig(pOBInit->Banks, pOBInit->WMSecStartSector, pOBInit->WMSecEndSector);
393 }
394 #endif /* __ARM_FEATURE_CMSE */
395
396 /* Boot Address configuration */
397 if ((pOBInit->OptionType & OPTIONBYTE_BOOTADDR) != 0U)
398 {
399 FLASH_OB_BootAddrConfig(pOBInit->BootConfig, pOBInit->BootAddr);
400 }
401
402 /* Unique boot entry point configuration */
403 if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U)
404 {
405 /* Configure the unique boot entry point */
406 FLASH_OB_BootLockConfig(pOBInit->BootConfig, pOBInit->BootLock);
407 }
408
409 /* OTP Block Lock configuration */
410 if ((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) != 0U)
411 {
412 FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock);
413 }
414
415 /* Hide Protection area configuration */
416 if ((pOBInit->OptionType & OPTIONBYTE_HDP) != 0U)
417 {
418 FLASH_OB_HDPConfig(pOBInit->Banks, pOBInit->HDPStartSector, pOBInit->HDPEndSector);
419 }
420
421 #if defined(FLASH_EDATAR_EDATA_EN)
422 /* Flash high-cycle data area configuration */
423 if ((pOBInit->OptionType & OPTIONBYTE_EDATA) != 0U)
424 {
425 FLASH_OB_EDATAConfig(pOBInit->Banks, pOBInit->EDATASize);
426 }
427 #endif /* FLASH_EDATAR_EDATA_EN */
428 }
429
430 /* Process Unlocked */
431 __HAL_UNLOCK(&pFlash);
432
433 return status;
434 }
435
436 /**
437 * @brief Get the Option byte configuration
438 * @param pOBInit pointer to an FLASH_OBInitStruct structure that
439 * contains the configuration information for the programming.
440 * @note The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2,
441 * as this parameter is use to get the given Bank WRP, PCROP and secured area configuration.
442 *
443 * @retval None
444 */
HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef * pOBInit)445 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
446 {
447 pOBInit->OptionType = (OPTIONBYTE_USER | OPTIONBYTE_PROD_STATE);
448
449 /* Get Product State */
450 pOBInit->ProductState = FLASH_OB_GetProdState();
451
452 /* Get the user option bytes */
453 FLASH_OB_GetUser(&(pOBInit->USERConfig), &(pOBInit->USERConfig2));
454
455 if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2))
456 {
457 /* Get write protection on the selected area */
458 pOBInit->OptionType |= OPTIONBYTE_WRP;
459 FLASH_OB_GetWRP(pOBInit->Banks, &(pOBInit->WRPState), &(pOBInit->WRPSector));
460
461 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
462 /* Get the configuration of the watermark secure area for the selected area */
463 pOBInit->OptionType |= OPTIONBYTE_WMSEC;
464 FLASH_OB_GetWMSEC(pOBInit->Banks, &(pOBInit->WMSecStartSector), &(pOBInit->WMSecEndSector));
465 #endif /* __ARM_FEATURE_CMSE */
466
467 /* Get the configuration of the hide protection for the selected area */
468 pOBInit->OptionType |= OPTIONBYTE_HDP;
469 FLASH_OB_GetHDP(pOBInit->Banks, &(pOBInit->HDPStartSector), &(pOBInit->HDPEndSector));
470 #if defined (FLASH_EDATAR_EDATA_EN)
471 /* Get the Flash high-cycle data configuration for the selected area */
472 pOBInit->OptionType |= OPTIONBYTE_EDATA;
473 FLASH_OB_GetEDATA(pOBInit->Banks, &(pOBInit->EDATASize));
474 #endif /* FLASH_EDATAR_EDATA_EN */
475 }
476
477 /* Get boot configuration */
478 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
479 if ((pOBInit->BootConfig == OB_BOOT_NS) || (pOBInit->BootConfig == OB_BOOT_SEC))
480 #else
481 if (pOBInit->BootConfig == OB_BOOT_NS)
482 #endif /* __ARM_FEATURE_CMSE */
483 {
484 pOBInit->OptionType |= OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK;
485 FLASH_OB_GetBootConfig(pOBInit->BootConfig, &(pOBInit->BootAddr), &(pOBInit->BootLock));
486 }
487
488 /* Get OTP Block Lock */
489 pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK;
490 pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock();
491 }
492
493 #if defined (FLASH_SR_OBKERR)
494 /**
495 * @brief Unlock the FLASH OBK register access
496 * @retval HAL Status
497 */
HAL_FLASHEx_OBK_Unlock(void)498 HAL_StatusTypeDef HAL_FLASHEx_OBK_Unlock(void)
499 {
500 HAL_StatusTypeDef status = HAL_OK;
501
502 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
503 if (READ_BIT(FLASH->SECOBKCFGR, FLASH_OBKCFGR_LOCK) != 0U)
504 {
505 /* Authorize the FLASH OBK Register access */
506 WRITE_REG(FLASH->SECOBKKEYR, FLASH_OBK_KEY1);
507 WRITE_REG(FLASH->SECOBKKEYR, FLASH_OBK_KEY2);
508
509 /* Verify Flash OBK Register is unlocked */
510 if (READ_BIT(FLASH->SECOBKCFGR, FLASH_OBKCFGR_LOCK) != 0U)
511 {
512 status = HAL_ERROR;
513 }
514 }
515 #else
516 if (READ_BIT(FLASH->NSOBKCFGR, FLASH_OBKCFGR_LOCK) != 0U)
517 {
518 /* Authorize the FLASH OBK Register access */
519 WRITE_REG(FLASH->NSOBKKEYR, FLASH_OBK_KEY1);
520 WRITE_REG(FLASH->NSOBKKEYR, FLASH_OBK_KEY2);
521
522 /* Verify Flash OBK Register is unlocked */
523 if (READ_BIT(FLASH->NSOBKCFGR, FLASH_OBKCFGR_LOCK) != 0U)
524 {
525 status = HAL_ERROR;
526 }
527 }
528 #endif /* __ARM_FEATURE_CMSE */
529
530 return status;
531 }
532
533 /**
534 * @brief Locks the FLASH OBK register access
535 * @retval HAL Status
536 */
HAL_FLASHEx_OBK_Lock(void)537 HAL_StatusTypeDef HAL_FLASHEx_OBK_Lock(void)
538 {
539 HAL_StatusTypeDef status = HAL_ERROR;
540
541 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
542 /* Set the LOCK Bit to lock the FLASH OBK Register access */
543 SET_BIT(FLASH->SECOBKCFGR, FLASH_OBKCFGR_LOCK);
544
545 /* verify Flash is locked */
546 if (READ_BIT(FLASH->SECOBKCFGR, FLASH_OBKCFGR_LOCK) != 0U)
547 {
548 status = HAL_OK;
549 }
550 #else
551 /* Set the LOCK Bit to lock the FLASH OBK Register access */
552 SET_BIT(FLASH->NSOBKCFGR, FLASH_OBKCFGR_LOCK);
553
554 /* Verify Flash OBK is locked */
555 if (READ_BIT(FLASH->NSOBKCFGR, FLASH_OBKCFGR_LOCK) != 0U)
556 {
557 status = HAL_OK;
558 }
559 #endif /* __ARM_FEATURE_CMSE */
560
561 return status;
562 }
563
564 /**
565 * @brief Swap the FLASH Option Bytes Keys (OBK)
566 * @param SwapOffset Specifies the number of keys to be swapped.
567 * This parameter can be a value between 0 (no OBK data swapped) and 511 (all OBK data swapped).
568 * Typical value are available in @ref FLASH_OBK_SWAP_Offset
569 * @retval HAL Status
570 */
HAL_FLASHEx_OBK_Swap(uint32_t SwapOffset)571 HAL_StatusTypeDef HAL_FLASHEx_OBK_Swap(uint32_t SwapOffset)
572 {
573 HAL_StatusTypeDef status;
574 __IO uint32_t *reg_obkcfgr;
575
576 /* Wait for last operation to be completed */
577 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
578
579 if (status == HAL_OK)
580 {
581 /* Access to SECOBKCFGR or NSOBKCFGR registers depends on operation type */
582 reg_obkcfgr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECOBKCFGR) : &(FLASH_NS->NSOBKCFGR);
583
584 /* Set OBK swap offset */
585 MODIFY_REG((*reg_obkcfgr), FLASH_OBKCFGR_SWAP_OFFSET, (SwapOffset << FLASH_OBKCFGR_SWAP_OFFSET_Pos));
586
587 /* Set OBK swap request */
588 SET_BIT((*reg_obkcfgr), FLASH_OBKCFGR_SWAP_SECT_REQ);
589
590 /* Wait for last operation to be completed */
591 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
592 }
593
594 return status;
595 }
596 /**
597 * @brief Swap the FLASH Option Bytes Keys (OBK) with interrupt enabled
598 * @param SwapOffset Specifies the number of keys to be swapped.
599 * This parameter can be a value between 0 (no OBK data swapped) and 511 (all OBK data swapped).
600 * Typical value are available in @ref FLASH_OBK_SWAP_Offset
601 * @retval HAL Status
602 */
HAL_FLASHEx_OBK_Swap_IT(uint32_t SwapOffset)603 HAL_StatusTypeDef HAL_FLASHEx_OBK_Swap_IT(uint32_t SwapOffset)
604 {
605 HAL_StatusTypeDef status;
606 __IO uint32_t *reg_obkcfgr;
607
608 /* Wait for last operation to be completed */
609 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
610
611 if (status == HAL_OK)
612 {
613 /* Access to SECOBKCFGR or NSOBKCFGR registers depends on operation type */
614 reg_obkcfgr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECOBKCFGR) : &(FLASH_NS->NSOBKCFGR);
615
616 /* Enable End of Operation and Error interrupts */
617 (*reg_obkcfgr) |= (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | FLASH_IT_STRBERR | FLASH_IT_INCERR);
618
619 /* Set OBK swap offset */
620 MODIFY_REG((*reg_obkcfgr), FLASH_OBKCFGR_SWAP_OFFSET, (SwapOffset << FLASH_OBKCFGR_SWAP_OFFSET_Pos));
621
622 /* Set OBK swap request */
623 SET_BIT((*reg_obkcfgr), FLASH_OBKCFGR_SWAP_SECT_REQ);
624 }
625
626 return status;
627 }
628 #endif /* FLASH_SR_OBKERR */
629
630 /**
631 * @brief Return the on-going Flash Operation. After a system reset, return
632 * the interrupted Flash operation, if any.
633 * @param pFlashOperation [out] pointer to a FLASH_OperationTypeDef structure
634 * that contains the Flash operation information.
635 * @retval None
636 */
HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef * pFlashOperation)637 void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation)
638 {
639 uint32_t opsr_reg = FLASH->OPSR;
640
641 /* Get Flash operation Type */
642 pFlashOperation->OperationType = opsr_reg & FLASH_OPSR_CODE_OP;
643
644 /* Get Flash operation memory */
645 #if defined (FLASH_EDATAR_EDATA_EN)
646 pFlashOperation->FlashArea = opsr_reg & (FLASH_OPSR_DATA_OP | FLASH_OPSR_BK_OP | \
647 FLASH_OPSR_SYSF_OP | FLASH_OPSR_OTP_OP);
648 #else
649 pFlashOperation->FlashArea = opsr_reg & (FLASH_OPSR_BK_OP | FLASH_OPSR_SYSF_OP | \
650 FLASH_OPSR_OTP_OP);
651 #endif /* FLASH_EDATAR_EDATA_EN */
652 /* Get Flash operation address */
653 pFlashOperation->Address = opsr_reg & FLASH_OPSR_ADDR_OP;
654 }
655
656 /**
657 * @}
658 */
659
660 /** @defgroup FLASHEx_Exported_Functions_Group2 FLASHEx Extension Protection configuration functions
661 * @brief Extension Protection configuration functions
662 * @{
663 */
664
665 /**
666 * @brief Configure the block-based secure area.
667 *
668 * @param pBBAttributes pointer to an FLASH_BBAttributesTypeDef structure that
669 * contains the configuration information for the programming.
670 *
671 * @note The field pBBAttributes->Bank should indicate which area is requested
672 * for the block-based attributes.
673 * @note The field pBBAttributes->BBAttributesType should indicate which
674 * block-base attribute type is requested: Secure or Privilege.
675 *
676 * @retval HAL Status
677 */
HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef * pBBAttributes)678 HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes)
679 {
680 HAL_StatusTypeDef status;
681 uint8_t index;
682 __IO uint32_t *reg;
683
684 /* Check the parameters */
685 assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank));
686 assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType));
687
688 /* Wait for last operation to be completed */
689 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
690
691 if (status == HAL_OK)
692 {
693 /* Set the first Block-Based register to write */
694 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
695 if (pBBAttributes->BBAttributesType == FLASH_BB_SEC)
696 {
697 if (pBBAttributes->Bank == FLASH_BANK_1)
698 {
699 reg = &(FLASH->SECBB1R1);
700 }
701 else
702 {
703 reg = &(FLASH->SECBB2R1);
704 }
705 }
706 else
707 #endif /* __ARM_FEATURE_CMSE */
708 {
709 if (pBBAttributes->Bank == FLASH_BANK_1)
710 {
711 reg = &(FLASH->PRIVBB1R1);
712 }
713 else
714 {
715 reg = &(FLASH->PRIVBB2R1);
716 }
717 }
718
719 /* Modify the register values and check that new attributes are taken in account */
720 for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++)
721 {
722 *reg = pBBAttributes->BBAttributes_array[index] & FLASH_PRIVBBR_PRIVBB;
723 if ((*reg) != (pBBAttributes->BBAttributes_array[index] & FLASH_PRIVBBR_PRIVBB))
724 {
725 status = HAL_ERROR;
726 }
727 reg++;
728 }
729
730 /* ISB instruction is called to be sure next instructions are performed with correct attributes */
731 __ISB();
732 }
733
734 /* Process Unlocked */
735 __HAL_UNLOCK(&pFlash);
736
737 return status;
738 }
739
740 /**
741 * @brief Return the block-based attributes.
742 *
743 * @param pBBAttributes [in/out] pointer to an FLASH_BBAttributesTypeDef structure
744 * that contains the configuration information.
745 * @note The field pBBAttributes->Bank should indicate which area is requested
746 * for the block-based attributes.
747 * @note The field pBBAttributes->BBAttributesType should indicate which
748 * block-base attribute type is requested: Secure or Privilege.
749 *
750 * @retval None
751 */
HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef * pBBAttributes)752 void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes)
753 {
754 uint8_t index;
755 __IO uint32_t *reg;
756
757 /* Check the parameters */
758 assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank));
759 assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType));
760
761 /* Set the first Block-Based register to read */
762 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
763 if (pBBAttributes->BBAttributesType == FLASH_BB_SEC)
764 {
765 if (pBBAttributes->Bank == FLASH_BANK_1)
766 {
767 reg = &(FLASH->SECBB1R1);
768 }
769 else
770 {
771 reg = &(FLASH->SECBB2R1);
772 }
773 }
774 else
775 #endif /* __ARM_FEATURE_CMSE */
776 {
777 if (pBBAttributes->Bank == FLASH_BANK_1)
778 {
779 reg = &(FLASH->PRIVBB1R1);
780 }
781 else
782 {
783 reg = &(FLASH->PRIVBB2R1);
784 }
785 }
786
787 /* Read the register values */
788 for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++)
789 {
790 pBBAttributes->BBAttributes_array[index] = (*reg) & FLASH_PRIVBBR_PRIVBB;
791 reg++;
792 }
793 }
794
795 /**
796 * @brief Configuration of the privilege attribute.
797 *
798 * @param PrivMode indicate privilege mode configuration
799 * This parameter can be one of the following values:
800 * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged or unprivileged access
801 * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied to unprivileged access
802 * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged or unprivileged access
803 * @arg FLASH_NSPRIV_DENIED: access to non-secure Flash registers is denied to unprivilege access
804 *
805 * @retval None
806 */
HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode)807 void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode)
808 {
809 /* Check the parameters */
810 assert_param(IS_FLASH_CFGPRIVMODE(PrivMode));
811 #if defined (FLASH_PRIVCFGR_SPRIV)
812 MODIFY_REG(FLASH->PRIVCFGR, (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV), PrivMode);
813 #else
814 MODIFY_REG(FLASH->PRIVCFGR, FLASH_PRIVCFGR_NSPRIV, PrivMode);
815 #endif /* FLASH_PRIVCFGR_SPRIV */
816 }
817
818 /**
819 * @brief Return the value of the privilege attribute.
820 *
821 * @retval It indicates the privilege mode configuration.
822 * This return value can be one of the following values:
823 * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged or unprivileged access
824 * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied to unprivileged access
825 * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged or unprivileged access
826 * @arg FLASH_NSPRIV_DENIED: access to Flash registers is denied to unprivilege accessP
827 */
HAL_FLASHEx_GetPrivMode(void)828 uint32_t HAL_FLASHEx_GetPrivMode(void)
829 {
830 #if defined (FLASH_PRIVCFGR_SPRIV)
831 return (FLASH->PRIVCFGR & (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV));
832 #else
833 return (FLASH->PRIVCFGR & FLASH_PRIVCFGR_NSPRIV);
834 #endif /* FLASH_PRIVCFGR_SPRIV */
835 }
836
837 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
838 /**
839 * @brief Configuration of the security inversion.
840 *
841 * @param SecInvState indicate the flash security state configuration
842 * This parameter can be one of the following values:
843 * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted
844 * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted
845 *
846 * @retval HAL Status
847 */
HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState)848 HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState)
849 {
850 HAL_StatusTypeDef status;
851
852 /* Check the parameters */
853 assert_param(IS_FLASH_CFGSECINV(SecInvState));
854
855 /* Process Locked */
856 __HAL_LOCK(&pFlash);
857
858 /* Wait for last operation to be completed */
859 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
860
861 if (status == HAL_OK)
862 {
863 MODIFY_REG(FLASH->SECCR, FLASH_CR_INV, SecInvState);
864 }
865
866 /* Process Unlocked */
867 __HAL_UNLOCK(&pFlash);
868
869 return status;
870 }
871
872 /**
873 * @brief Return the value of the security inversion.
874 *
875 * @retval It indicates the flash security state configuration
876 * This return value can be one of the following values:
877 * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted
878 * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted
879 */
HAL_FLASHEx_GetSecInversion(void)880 uint32_t HAL_FLASHEx_GetSecInversion(void)
881 {
882 return (FLASH->SECCR & FLASH_CR_INV);
883 }
884 #endif /* __ARM_FEATURE_CMSE */
885
886 /**
887 * @brief Configure the HDP extension area.
888 *
889 * @param pHDPExtension pointer to an FLASH_HDPExtentionTypeDef structure that
890 * contains the configuration information.
891 *
892 * @note The field pHDPExtension->Banks should indicate which area is requested
893 * for the HDP extension.
894 * @note The field pHDPExtension->NbSectors should indicate the number of
895 * sector to be added to the HDP area.
896 *
897 * @retval HAL Status
898 */
HAL_FLASHEx_ConfigHDPExtension(const FLASH_HDPExtensionTypeDef * pHDPExtension)899 HAL_StatusTypeDef HAL_FLASHEx_ConfigHDPExtension(const FLASH_HDPExtensionTypeDef *pHDPExtension)
900 {
901 /* Check the parameters */
902 assert_param(IS_FLASH_BANK(pHDPExtension->Banks));
903 assert_param(IS_FLASH_SECTOR(pHDPExtension->NbSectors));
904
905 /* Set the HDP extension register */
906 if (pHDPExtension->Banks == FLASH_BANK_1)
907 {
908 MODIFY_REG(FLASH->HDPEXTR, FLASH_HDPEXTR_HDP1_EXT, pHDPExtension->NbSectors);
909 }
910 else if (pHDPExtension->Banks == FLASH_BANK_2)
911 {
912 MODIFY_REG(FLASH->HDPEXTR, FLASH_HDPEXTR_HDP2_EXT, (pHDPExtension->NbSectors << FLASH_HDPEXTR_HDP2_EXT_Pos));
913 }
914 else
915 {
916 FLASH->HDPEXTR = (pHDPExtension->NbSectors << FLASH_HDPEXTR_HDP2_EXT_Pos) | pHDPExtension->NbSectors;
917 }
918
919 return HAL_OK;
920 }
921
922 /**
923 * @}
924 */
925
926 /**
927 * @}
928 */
929
930 /* Private functions ---------------------------------------------------------*/
931
932 /** @addtogroup FLASHEx_Private_Functions
933 * @{
934 */
935
936 /**
937 * @brief Mass erase of FLASH memory
938 * @param Banks Banks to be erased
939 * This parameter can be one of the following values:
940 * @arg FLASH_BANK_1: Bank1 to be erased
941 * @arg FLASH_BANK_2: Bank2 to be erased
942 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
943 * @retval None
944 */
FLASH_MassErase(uint32_t Banks)945 static void FLASH_MassErase(uint32_t Banks)
946 {
947 __IO uint32_t *reg_cr;
948
949 /* Check the parameters */
950 assert_param(IS_FLASH_BANK(Banks));
951
952 /* Access to SECCR or NSCR registers depends on operation type */
953 #if defined (FLASH_OPTSR2_TZEN)
954 reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
955 #else
956 reg_cr = &(FLASH_NS->NSCR);
957 #endif /* FLASH_OPTSR2_TZEN */
958
959 /* Flash Mass Erase */
960 if ((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH)
961 {
962 /* Set Mass Erase Bit */
963 SET_BIT((*reg_cr), FLASH_CR_MER | FLASH_CR_START);
964 }
965 else
966 {
967 /* Proceed to erase Flash Bank */
968 if ((Banks & FLASH_BANK_1) == FLASH_BANK_1)
969 {
970 /* Erase Bank1 */
971 MODIFY_REG((*reg_cr), (FLASH_CR_BKSEL | FLASH_CR_BER | FLASH_CR_START), (FLASH_CR_BER | FLASH_CR_START));
972 }
973
974 if ((Banks & FLASH_BANK_2) == FLASH_BANK_2)
975 {
976 /* Erase Bank2 */
977 SET_BIT((*reg_cr), (FLASH_CR_BER | FLASH_CR_BKSEL | FLASH_CR_START));
978 }
979 }
980 }
981
982 /**
983 * @brief Erase the specified FLASH memory sector
984 * @param Sector FLASH sector to erase
985 * This parameter can be a value of @ref FLASH_Sectors
986 * @param Banks Bank(s) where the sector will be erased
987 * This parameter can be one of the following values:
988 * @arg FLASH_BANK_1: Sector in bank 1 to be erased
989 * @arg FLASH_BANK_2: Sector in bank 2 to be erased
990 * @retval None
991 */
FLASH_Erase_Sector(uint32_t Sector,uint32_t Banks)992 void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks)
993 {
994 __IO uint32_t *reg_cr;
995
996 /* Check the parameters */
997 assert_param(IS_FLASH_SECTOR(Sector));
998 assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
999
1000 /* Access to SECCR or NSCR registers depends on operation type */
1001 #if defined (FLASH_OPTSR2_TZEN)
1002 reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
1003 #else
1004 reg_cr = &(FLASH_NS->NSCR);
1005 #endif /* FLASH_OPTSR2_TZEN */
1006
1007 if ((Banks & FLASH_BANK_1) == FLASH_BANK_1)
1008 {
1009 /* Reset Sector Number for Bank1 */
1010 (*reg_cr) &= ~(FLASH_CR_SNB | FLASH_CR_BKSEL);
1011
1012 (*reg_cr) |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
1013 }
1014 else
1015 {
1016 /* Reset Sector Number for Bank2 */
1017 (*reg_cr) &= ~(FLASH_CR_SNB);
1018
1019 (*reg_cr) |= (FLASH_CR_SER | FLASH_CR_BKSEL | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
1020 }
1021 }
1022
1023 #if defined (FLASH_SR_OBKERR)
1024 /**
1025 * @brief Erase of FLASH OBK
1026 * @retval None
1027 */
FLASH_OBKErase()1028 static void FLASH_OBKErase()
1029 {
1030 __IO uint32_t *reg_obkcfgr;
1031
1032 /* Access to SECOBKCFGR or NSOBKCFGR registers depends on operation type */
1033 reg_obkcfgr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECOBKCFGR) : &(FLASH_NS->NSOBKCFGR);
1034
1035 /* Set OBK Erase Bit */
1036 SET_BIT((*reg_obkcfgr), FLASH_OBKCFGR_ALT_SECT_ERASE);
1037 }
1038 #endif /* FLASH_SR_OBKERR */
1039
1040 /**
1041 * @brief Enable the write protection of the desired bank1 or bank 2 sectors
1042 * @param WRPSector specifies the sectors to be write protected.
1043 * This parameter can be a value of @ref FLASH_OB_Write_Protection_Sectors
1044 *
1045 * @param Banks the specific bank to apply WRP sectors
1046 * This parameter can be one of the following values:
1047 * @arg FLASH_BANK_1: enable WRP on specified bank1 sectors
1048 * @arg FLASH_BANK_2: enable WRP on specified bank2 sectors
1049 * @arg FLASH_BANK_BOTH: enable WRP on both bank1 and bank2 specified sectors
1050 *
1051 * @retval None
1052 */
FLASH_OB_EnableWRP(uint32_t WRPSector,uint32_t Banks)1053 static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
1054 {
1055 /* Check the parameters */
1056 assert_param(IS_FLASH_BANK(Banks));
1057
1058 if ((Banks & FLASH_BANK_1) == FLASH_BANK_1)
1059 {
1060 /* Enable Write Protection for bank 1 */
1061 FLASH->WRP1R_PRG &= (~(WRPSector & FLASH_WRPR_WRPSG));
1062 }
1063
1064 if ((Banks & FLASH_BANK_2) == FLASH_BANK_2)
1065 {
1066 /* Enable Write Protection for bank 2 */
1067 FLASH->WRP2R_PRG &= (~(WRPSector & FLASH_WRPR_WRPSG));
1068 }
1069 }
1070
1071 /**
1072 * @brief Disable the write protection of the desired bank1 or bank 2 sectors
1073 * @param WRPSector specifies the sectors to disable write protection.
1074 * This parameter can be a value of @ref FLASH_OB_Write_Protection_Sectors
1075 *
1076 * @param Banks the specific bank to apply WRP sectors
1077 * This parameter can be one of the following values:
1078 * @arg FLASH_BANK_1: disable WRP on specified bank1 sectors
1079 * @arg FLASH_BANK_2: disable WRP on specified bank2 sectors
1080 * @arg FLASH_BANK_BOTH: disable WRP on both bank1 and bank2 specified sectors
1081 *
1082 * @retval None
1083 */
FLASH_OB_DisableWRP(uint32_t WRPSector,uint32_t Banks)1084 static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
1085 {
1086 /* Check the parameters */
1087 assert_param(IS_FLASH_BANK(Banks));
1088
1089 if ((Banks & FLASH_BANK_1) == FLASH_BANK_1)
1090 {
1091 /* Disable Write Protection for bank 1 */
1092 FLASH->WRP1R_PRG |= (WRPSector & FLASH_WRPR_WRPSG);
1093 }
1094
1095 if ((Banks & FLASH_BANK_2) == FLASH_BANK_2)
1096 {
1097 /* Disable Write Protection for bank 2 */
1098 FLASH->WRP2R_PRG |= (WRPSector & FLASH_WRPR_WRPSG);
1099 }
1100 }
1101
1102 /**
1103 * @brief Get the write protection of the given bank 1 or bank 2 sectors
1104 * @param[in] Bank specifies the bank where to get the write protection sectors.
1105 * This parameter can be exclusively one of the following values:
1106 * @arg FLASH_BANK_1: Get bank1 WRP sectors
1107 * @arg FLASH_BANK_2: Get bank2 WRP sectors
1108 *
1109 * @param[out] WRPState returns the write protection state of the returned sectors.
1110 * This parameter can be one of the following values:
1111 * @arg WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE
1112
1113 * @param[out] WRPSector returns the write protected sectors on the given bank .
1114 * This parameter can be a value of @ref FLASH_OB_Write_Protection_Sectors
1115 *
1116 * @retval None
1117 */
FLASH_OB_GetWRP(uint32_t Bank,uint32_t * WRPState,uint32_t * WRPSector)1118 static void FLASH_OB_GetWRP(uint32_t Bank, uint32_t *WRPState, uint32_t *WRPSector)
1119 {
1120 uint32_t regvalue = 0U;
1121
1122 if (Bank == FLASH_BANK_1)
1123 {
1124 regvalue = FLASH->WRP1R_CUR;
1125 }
1126
1127 if (Bank == FLASH_BANK_2)
1128 {
1129 regvalue = FLASH->WRP2R_CUR;
1130 }
1131
1132 (*WRPSector) = (~regvalue) & FLASH_WRPR_WRPSG;
1133
1134 if (*WRPSector == 0U)
1135 {
1136 (*WRPState) = OB_WRPSTATE_DISABLE;
1137 }
1138 else
1139 {
1140 (*WRPState) = OB_WRPSTATE_ENABLE;
1141 }
1142 }
1143
1144 /**
1145 * @brief Set the product state.
1146 *
1147 * @note To configure the product state, the option lock bit OPTLOCK must be
1148 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
1149 * @note To validate the product state, the option bytes must be reloaded
1150 * through the call of the HAL_FLASH_OB_Launch() function.
1151 *
1152 * @param ProductState specifies the product state.
1153 * This parameter can be a value of @ref FLASH_OB_Product_State
1154 *
1155 * @retval None
1156 */
FLASH_OB_ProdStateConfig(uint32_t ProductState)1157 static void FLASH_OB_ProdStateConfig(uint32_t ProductState)
1158 {
1159 /* Check the parameters */
1160 assert_param(IS_OB_PRODUCT_STATE(ProductState));
1161
1162 /* Configure the Product State in the option bytes register */
1163 MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_PRODUCT_STATE, ProductState);
1164 }
1165
1166 /**
1167 * @brief Get the the product state.
1168 * @retval ProductState returns the product state.
1169 * This returned value can a value of @ref FLASH_OB_Product_State
1170 */
FLASH_OB_GetProdState(void)1171 static uint32_t FLASH_OB_GetProdState(void)
1172 {
1173 return (FLASH->OPTSR_CUR & FLASH_OPTSR_PRODUCT_STATE);
1174 }
1175
1176 /**
1177 * @brief Program the FLASH User Option Byte.
1178 *
1179 * @note To configure the user option bytes, the option lock bit OPTLOCK must
1180 * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
1181 * @note To validate the user option bytes, the option bytes must be reloaded
1182 * through the call of the HAL_FLASH_OB_Launch() function.
1183 *
1184 * @param UserType specifies The FLASH User Option Bytes to be modified.
1185 * This parameter can be a combination of @ref FLASH_OB_USER_Type
1186 *
1187 * @param UserConfig1 specifies values of the selected User Option Bytes.
1188 * This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
1189 * @ref FLASH_OB_USER_BORH_EN, @ref FLASH_OB_USER_IWDG_SW,
1190 * @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nRST_STOP,
1191 * @ref FLASH_OB_USER_nRST_STANDBY, @ref FLASH_OB_USER_IO_VDD_HSLV,
1192 * @ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_IWDG_STOP,
1193 * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_BOOT_UBE and @ref OB_USER_SWAP_BANK.
1194 * @param UserConfig2 specifies values of the selected User Option Bytes.
1195 * @ref FLASH_OB_USER_SRAM1_3_RST, @ref FLASH_OB_USER_SRAM2_RST,
1196 * @ref FLASH_OB_USER_BKPRAM_ECC, @ref FLASH_OB_USER_SRAM3_ECC,
1197 * @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM1_ECC,
1198 * @ref FLASH_OB_USER_SRAM1_RST and @ref OB_USER_TZEN.
1199 * @retval None
1200 */
FLASH_OB_UserConfig(uint32_t UserType,uint32_t UserConfig1,uint32_t UserConfig2)1201 static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig1, uint32_t UserConfig2)
1202 {
1203 uint32_t optr_reg1_val = 0U;
1204 uint32_t optr_reg1_mask = 0U;
1205 uint32_t optr_reg2_val = 0U;
1206 uint32_t optr_reg2_mask = 0U;
1207
1208 /* Check the parameters */
1209 assert_param(IS_OB_USER_TYPE(UserType));
1210
1211 if ((UserType & OB_USER_BOR_LEV) != 0U)
1212 {
1213 /* BOR level option byte should be modified */
1214 assert_param(IS_OB_USER_BOR_LEVEL(UserConfig1 & FLASH_OPTSR_BOR_LEV));
1215
1216 /* Set value and mask for BOR level option byte */
1217 optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_BOR_LEV);
1218 optr_reg1_mask |= FLASH_OPTSR_BOR_LEV;
1219 }
1220
1221 if ((UserType & OB_USER_BORH_EN) != 0U)
1222 {
1223 /* BOR high enable status bit should be modified */
1224 assert_param(IS_OB_USER_BORH_EN(UserConfig1 & FLASH_OPTSR_BORH_EN));
1225
1226 /* Set value and mask for BOR high enable status bit */
1227 optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_BORH_EN);
1228 optr_reg1_mask |= FLASH_OPTSR_BORH_EN;
1229 }
1230
1231 if ((UserType & OB_USER_IWDG_SW) != 0U)
1232 {
1233 /* IWDG_SW option byte should be modified */
1234 assert_param(IS_OB_USER_IWDG(UserConfig1 & FLASH_OPTSR_IWDG_SW));
1235
1236 /* Set value and mask for IWDG_SW option byte */
1237 optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_IWDG_SW);
1238 optr_reg1_mask |= FLASH_OPTSR_IWDG_SW;
1239 }
1240
1241 if ((UserType & OB_USER_WWDG_SW) != 0U)
1242 {
1243 /* WWDG_SW option byte should be modified */
1244 assert_param(IS_OB_USER_WWDG(UserConfig1 & FLASH_OPTSR_WWDG_SW));
1245
1246 /* Set value and mask for WWDG_SW option byte */
1247 optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_WWDG_SW);
1248 optr_reg1_mask |= FLASH_OPTSR_WWDG_SW;
1249 }
1250
1251 if ((UserType & OB_USER_NRST_STOP) != 0U)
1252 {
1253 /* nRST_STOP option byte should be modified */
1254 assert_param(IS_OB_USER_STOP(UserConfig1 & FLASH_OPTSR_NRST_STOP));
1255
1256 /* Set value and mask for nRST_STOP option byte */
1257 optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_NRST_STOP);
1258 optr_reg1_mask |= FLASH_OPTSR_NRST_STOP;
1259 }
1260
1261 if ((UserType & OB_USER_NRST_STDBY) != 0U)
1262 {
1263 /* nRST_STDBY option byte should be modified */
1264 assert_param(IS_OB_USER_STANDBY(UserConfig1 & FLASH_OPTSR_NRST_STDBY));
1265
1266 /* Set value and mask for nRST_STDBY option byte */
1267 optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_NRST_STDBY);
1268 optr_reg1_mask |= FLASH_OPTSR_NRST_STDBY;
1269 }
1270
1271 if ((UserType & OB_USER_IO_VDD_HSLV) != 0U)
1272 {
1273 /* IO_VDD_HSLV option byte should be modified */
1274 assert_param(IS_OB_USER_IO_VDD_HSLV(UserConfig1 & FLASH_OPTSR_IO_VDD_HSLV));
1275
1276 /* Set value and mask for IO_VDD_HSLV option byte */
1277 optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_IO_VDD_HSLV);
1278 optr_reg1_mask |= FLASH_OPTSR_IO_VDD_HSLV;
1279 }
1280
1281 if ((UserType & OB_USER_IO_VDDIO2_HSLV) != 0U)
1282 {
1283 /* IO_VDD_HSLV option byte should be modified */
1284 assert_param(IS_OB_USER_IO_VDDIO2_HSLV(UserConfig1 & FLASH_OPTSR_IO_VDDIO2_HSLV));
1285
1286 /* Set value and mask for IO_VDD_HSLV option byte */
1287 optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_IO_VDDIO2_HSLV);
1288 optr_reg1_mask |= FLASH_OPTSR_IO_VDDIO2_HSLV;
1289 }
1290
1291 if ((UserType & OB_USER_IWDG_STOP) != 0U)
1292 {
1293 /* IWDG_STOP option byte should be modified */
1294 assert_param(IS_OB_USER_IWDG_STOP(UserConfig1 & FLASH_OPTSR_IWDG_STOP));
1295
1296 /* Set value and mask for IWDG_STOP option byte */
1297 optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_IWDG_STOP);
1298 optr_reg1_mask |= FLASH_OPTSR_IWDG_STOP;
1299 }
1300
1301 if ((UserType & OB_USER_IWDG_STDBY) != 0U)
1302 {
1303 /* IWDG_STDBY option byte should be modified */
1304 assert_param(IS_OB_USER_IWDG_STDBY(UserConfig1 & FLASH_OPTSR_IWDG_STDBY));
1305
1306 /* Set value and mask for IWDG_STDBY option byte */
1307 optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_IWDG_STDBY);
1308 optr_reg1_mask |= FLASH_OPTSR_IWDG_STDBY;
1309 }
1310
1311 #if defined (FLASH_OPTSR_BOOT_UBE)
1312 if ((UserType & OB_USER_BOOT_UBE) != 0U)
1313 {
1314 /* SWAP_BANK option byte should be modified */
1315 assert_param(IS_OB_USER_BOOT_UBE(UserConfig1 & FLASH_OPTSR_BOOT_UBE));
1316
1317 /* Set value and mask for BOOT_UBE option byte */
1318 optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_BOOT_UBE);
1319 optr_reg1_mask |= FLASH_OPTSR_BOOT_UBE;
1320 }
1321 #endif /* FLASH_OPTSR_BOOT_UBE */
1322
1323 if ((UserType & OB_USER_SWAP_BANK) != 0U)
1324 {
1325 /* SWAP_BANK option byte should be modified */
1326 assert_param(IS_OB_USER_SWAP_BANK(UserConfig1 & FLASH_OPTSR_SWAP_BANK));
1327
1328 /* Set value and mask for SWAP_BANK option byte */
1329 optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_SWAP_BANK);
1330 optr_reg1_mask |= FLASH_OPTSR_SWAP_BANK;
1331 }
1332
1333 #if defined (FLASH_OPTSR2_SRAM1_3_RST)
1334 if ((UserType & OB_USER_SRAM1_3_RST) != 0U)
1335 {
1336 /* SRAM13_RST option byte should be modified */
1337 assert_param(IS_OB_USER_SRAM1_3_RST(UserConfig2 & FLASH_OPTSR2_SRAM1_3_RST));
1338
1339 /* Set value and mask for SRAM13_RST option byte */
1340 optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_SRAM1_3_RST);
1341 optr_reg2_mask |= FLASH_OPTSR2_SRAM1_3_RST;
1342 }
1343 #endif /* FLASH_OPTSR2_SRAM1_3_RST */
1344
1345 #if defined (FLASH_OPTSR2_SRAM1_RST)
1346 if ((UserType & OB_USER_SRAM1_RST) != 0U)
1347 {
1348 /* SRAM1_RST option byte should be modified */
1349 assert_param(IS_OB_USER_SRAM1_RST(UserConfig2 & FLASH_OPTSR2_SRAM1_RST));
1350
1351 /* Set value and mask for SRAM1_RST option byte */
1352 optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_SRAM1_RST);
1353 optr_reg2_mask |= FLASH_OPTSR2_SRAM1_RST;
1354 }
1355 #endif /* FLASH_OPTSR2_SRAM1_RST */
1356
1357 if ((UserType & OB_USER_SRAM2_RST) != 0U)
1358 {
1359 /* SRAM2_RST option byte should be modified */
1360 assert_param(IS_OB_USER_SRAM2_RST(UserConfig2 & FLASH_OPTSR2_SRAM2_RST));
1361
1362 /* Set value and mask for SRAM2_RST option byte */
1363 optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_SRAM2_RST);
1364 optr_reg2_mask |= FLASH_OPTSR2_SRAM2_RST;
1365 }
1366
1367 if ((UserType & OB_USER_BKPRAM_ECC) != 0U)
1368 {
1369 /* BKPRAM_ECC option byte should be modified */
1370 assert_param(IS_OB_USER_BKPRAM_ECC(UserConfig2 & FLASH_OPTSR2_BKPRAM_ECC));
1371
1372 /* Set value and mask for BKPRAM_ECC option byte */
1373 optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_BKPRAM_ECC);
1374 optr_reg2_mask |= FLASH_OPTSR2_BKPRAM_ECC;
1375 }
1376
1377 #if defined (FLASH_OPTSR2_SRAM3_ECC)
1378 if ((UserType & OB_USER_SRAM3_ECC) != 0U)
1379 {
1380 /* SRAM3_ECC option byte should be modified */
1381 assert_param(IS_OB_USER_SRAM3_ECC(UserConfig2 & FLASH_OPTSR2_SRAM3_ECC));
1382
1383 /* Set value and mask for SRAM3_ECC option byte */
1384 optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_SRAM3_ECC);
1385 optr_reg2_mask |= FLASH_OPTSR2_SRAM3_ECC;
1386 }
1387 #endif /* FLASH_OPTSR2_SRAM3_ECC */
1388
1389 if ((UserType & OB_USER_SRAM2_ECC) != 0U)
1390 {
1391 /* SRAM2_ECC option byte should be modified */
1392 assert_param(IS_OB_USER_SRAM2_ECC(UserConfig2 & FLASH_OPTSR2_SRAM2_ECC));
1393
1394 /* Set value and mask for SRAM2_ECC option byte */
1395 optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_SRAM2_ECC);
1396 optr_reg2_mask |= FLASH_OPTSR2_SRAM2_ECC;
1397 }
1398
1399 #if defined (FLASH_OPTSR2_SRAM1_ECC)
1400 if ((UserType & OB_USER_SRAM1_ECC) != 0U)
1401 {
1402 /* SRAM2_ECC option byte should be modified */
1403 assert_param(IS_OB_USER_SRAM1_ECC(UserConfig2 & FLASH_OPTSR2_SRAM1_ECC));
1404
1405 /* Set value and mask for SRAM2_ECC option byte */
1406 optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_SRAM1_ECC);
1407 optr_reg2_mask |= FLASH_OPTSR2_SRAM1_ECC;
1408 }
1409 #endif /* FLASH_OPTSR2_SRAM1_ECC */
1410
1411 #if defined (FLASH_OPTSR2_USBPD_DIS)
1412 if ((UserType & OB_USER_USBPD_DIS) != 0U)
1413 {
1414 /* USBPD_DIS option byte should be modified */
1415 assert_param(IS_OB_USER_USBPD_DIS(UserConfig2 & FLASH_OPTSR2_USBPD_DIS));
1416
1417 /* Set value and mask for USBPD_DIS option byte */
1418 optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_USBPD_DIS);
1419 optr_reg2_mask |= FLASH_OPTSR2_USBPD_DIS;
1420 }
1421 #endif /* FLASH_OPTSR2_USBPD_DIS */
1422
1423 #if defined (FLASH_OPTSR2_TZEN)
1424 if ((UserType & OB_USER_TZEN) != 0U)
1425 {
1426 /* TZEN option byte should be modified */
1427 assert_param(IS_OB_USER_TZEN(UserConfig2 & FLASH_OPTSR2_TZEN));
1428
1429 /* Set value and mask for TZEN option byte */
1430 optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_TZEN);
1431 optr_reg2_mask |= FLASH_OPTSR2_TZEN;
1432 }
1433 #endif /* FLASH_OPTSR2_TZEN */
1434
1435 /* Check to write first User OB register or/and second one */
1436 if ((UserType & 0xFFFU) != 0U)
1437 {
1438 /* Configure the option bytes register */
1439 MODIFY_REG(FLASH->OPTSR_PRG, optr_reg1_mask, optr_reg1_val);
1440 }
1441 if ((UserType & 0xFF000U) != 0U)
1442 {
1443 /* Configure the option bytes register */
1444 MODIFY_REG(FLASH->OPTSR2_PRG, optr_reg2_mask, optr_reg2_val);
1445 }
1446 }
1447
1448 /**
1449 * @brief Return the FLASH User Option Byte values.
1450 * @param UserConfig1 FLASH User Option Bytes values
1451 * 2M: IWDG_SW(Bit3), WWDG_SW(Bit4), nRST_STOP(Bit 6), nRST_STDY(Bit 7),
1452 * PRODUCT_STATE(Bit[8:15]), IO_VDD_HSLV(Bit 16), IO_VDDTO2_HSLV(Bit 17),
1453 * IWDG_STOP(Bit 20), IWDG_STDBY (Bit 21), BOOT_UBE(Bit[22:29]) and SWAP_BANK(Bit 31).
1454 * 128K: IWDG_SW(Bit3), WWDG_SW(Bit4), nRST_STOP(Bit 6), nRST_STDY(Bit 7),
1455 * PRODUCT_STATE(Bit[8:15]), IO_VDD_HSLV(Bit16), IO_VDDIO2_HSLV(Bit17), IWDG_STOP(Bit 20),
1456 * IWDG_STDBY (Bit 21) and SWAP_BANK(Bit 31).
1457 * @param UserConfig2 FLASH User Option Bytes values
1458 * 2M: SRAM1_3_RST(Bit2), SRAM2_RST(Bit 3), BKPRAM_ECC(Bit 4), SRAM3_ECC(Bit 5),
1459 * SRAM2_ECC(Bit 6).
1460 * 128K: SRAM2_RST(Bit 3), BKPRAM_ECC(Bit 4), SRAM2_ECC(Bit 6),
1461 * SRAM1_RST(Bit9), SRAM1_ECC(Bit10).
1462 * @retval None
1463 */
FLASH_OB_GetUser(uint32_t * UserConfig1,uint32_t * UserConfig2)1464 static void FLASH_OB_GetUser(uint32_t *UserConfig1, uint32_t *UserConfig2)
1465 {
1466 (*UserConfig1) = FLASH->OPTSR_CUR & (~FLASH_OPTSR_PRODUCT_STATE);
1467
1468 (*UserConfig2) = FLASH->OPTSR2_CUR;
1469 }
1470
1471 /**
1472 * @brief Configure Boot address
1473 * @param BootOption specifies the Boot address option byte to be programmed.
1474 * This parameter can be one of the following values:
1475 * @arg OB_BOOTADDR_NS: Non-secure boot address
1476 * @arg OB_BOOTADDR_SEC: Secure boot address
1477 * @param BootAddress: specifies the boot address value
1478 * This parameter can be sector number between 0 and 0xFFFFFF00
1479 * @retval None
1480 */
FLASH_OB_BootAddrConfig(uint32_t BootOption,uint32_t BootAddress)1481 static void FLASH_OB_BootAddrConfig(uint32_t BootOption, uint32_t BootAddress)
1482 {
1483 /* Check the parameters */
1484 assert_param(IS_OB_BOOT_CONFIG(BootOption));
1485
1486 if (BootOption == OB_BOOT_NS)
1487 {
1488 MODIFY_REG(FLASH->NSBOOTR_PRG, FLASH_BOOTR_BOOTADD, BootAddress);
1489 }
1490 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1491 else if (BootOption == OB_BOOT_SEC)
1492 {
1493 MODIFY_REG(FLASH->SECBOOTR_PRG, FLASH_BOOTR_BOOTADD, BootAddress);
1494 }
1495 #endif /* __ARM_FEATURE_CMSE */
1496 else
1497 {
1498 /* Empty statement (to be compliant MISRA 15.7) */
1499 }
1500 }
1501
1502 /**
1503 * @brief Configure the boot lock.
1504 *
1505 * @param BootOption select the BOOT_LOCK option: secure or non-secure.
1506 * This parameter can be one of the following values:
1507 * @arg OB_BOOT_LOCK_SEC: Boot Lock mode deactivated
1508 * @arg OB_BOOT_LOCK_NS: Boot Lock mode activated
1509 *
1510 * @param BootLockConfig specifies the activation of the BOOT_LOCK.
1511 * This parameter can be one of the following values:
1512 * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated
1513 * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated
1514 *
1515 * @retval None
1516 */
FLASH_OB_BootLockConfig(uint32_t BootOption,uint32_t BootLockConfig)1517 static void FLASH_OB_BootLockConfig(uint32_t BootOption, uint32_t BootLockConfig)
1518 {
1519 /* Check the parameters */
1520 assert_param(IS_OB_BOOT_CONFIG(BootOption));
1521 assert_param(IS_OB_BOOT_LOCK(BootLockConfig));
1522
1523 /* Configure the option bytes register */
1524 if (BootOption == OB_BOOT_NS)
1525 {
1526 MODIFY_REG(FLASH->NSBOOTR_PRG, FLASH_BOOTR_BOOT_LOCK, BootLockConfig);
1527 }
1528 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1529 else if (BootOption == OB_BOOT_SEC)
1530 {
1531 MODIFY_REG(FLASH->SECBOOTR_PRG, FLASH_BOOTR_BOOT_LOCK, BootLockConfig);
1532 }
1533 #endif /* __ARM_FEATURE_CMSE */
1534 else
1535 {
1536 /* Empty statement (to be compliant MISRA 15.7) */
1537 }
1538 }
1539
1540 /**
1541 * @brief Get the boot configuration
1542 * @param[in] BootOption specifies the boot address option byte to be returned.
1543 * This parameter can be one of the following values:
1544 * @arg OB_BOOT_NS: Non-secure boot address
1545 * @arg OB_BOOT_SEC: Secure boot address
1546 *
1547 * @param[out] BootAddress specifies the boot address value
1548 *
1549 * @param[out] BootLockConfig returns the activation of the BOOT_LOCK.
1550 * This parameter can be one of the following values:
1551 * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated
1552 * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated
1553 * @retval None
1554 */
FLASH_OB_GetBootConfig(uint32_t BootOption,uint32_t * BootAddress,uint32_t * BootLockConfig)1555 static void FLASH_OB_GetBootConfig(uint32_t BootOption, uint32_t *BootAddress, uint32_t *BootLockConfig)
1556 {
1557 if (BootOption == OB_BOOT_NS)
1558 {
1559 *BootAddress = FLASH->NSBOOTR_CUR & FLASH_BOOTR_BOOTADD;
1560 *BootLockConfig = FLASH->NSBOOTR_CUR & FLASH_BOOTR_BOOT_LOCK;
1561 }
1562 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1563 else if (BootOption == OB_BOOT_SEC)
1564 {
1565 *BootAddress = (FLASH->SECBOOTR_CUR & FLASH_BOOTR_BOOTADD);
1566 *BootLockConfig = (FLASH->SECBOOTR_CUR & FLASH_BOOTR_BOOT_LOCK);
1567 }
1568 #endif /* __ARM_FEATURE_CMSE */
1569 else
1570 {
1571 /* Empty statement (to be compliant MISRA 15.7) */
1572 }
1573 }
1574
1575 /**
1576 * @brief Configure the OTP Block Lock.
1577 * @param OTP_Block specifies the OTP Block to lock.
1578 * This parameter can be a value of @ref FLASH_OTP_Blocks
1579 * @retval None
1580 */
FLASH_OB_OTP_LockConfig(uint32_t OTP_Block)1581 static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block)
1582 {
1583 /* Configure the OTP Block lock in the option bytes register */
1584 FLASH->OTPBLR_PRG |= OTP_Block;
1585 }
1586
1587 /**
1588 * @brief Get the OTP Block Lock.
1589 * @retval OTP_Block specifies the OTP Block to lock.
1590 * This return value can be a value of @ref FLASH_OTP_Blocks
1591 */
FLASH_OB_OTP_GetLock(void)1592 static uint32_t FLASH_OB_OTP_GetLock(void)
1593 {
1594 return (FLASH->OTPBLR_CUR);
1595 }
1596
1597 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1598 /**
1599 * @brief Configure the watermark-based secure area.
1600 *
1601 * @param Banks specifies the bank where to apply Watermark protection
1602 * This parameter can be one of the following values:
1603 * @arg FLASH_BANK_1: configure Watermark on bank1
1604 * @arg FLASH_BANK_2: configure Watermark on bank2
1605 * @arg FLASH_BANK_BOTH: configure Watermark on both bank1 and bank2
1606 *
1607 * @param WMSecStartSector specifies the start sector of the secure area
1608 * This parameter can be sector number between 0 and (max number of sectors in the bank - 1)
1609 *
1610 * @param WMSecEndSector specifies the end sector of the secure area
1611 * This parameter can be sector number between WMSecStartSector and WMSecEndSector(max number of sectors
1612 * in the bank - 1)
1613 *
1614 * @retval None
1615 */
FLASH_OB_WMSECConfig(uint32_t Banks,uint32_t WMSecStartSector,uint32_t WMSecEndSector)1616 static void FLASH_OB_WMSECConfig(uint32_t Banks, uint32_t WMSecStartSector, uint32_t WMSecEndSector)
1617 {
1618 /* Check the parameters */
1619 assert_param(IS_FLASH_BANK(Banks));
1620 assert_param(IS_FLASH_SECTOR(WMSecStartSector));
1621 assert_param(IS_FLASH_SECTOR(WMSecEndSector));
1622
1623 /* Write SECWM registers */
1624 if ((Banks & FLASH_BANK_1) == FLASH_BANK_1)
1625 {
1626 /* Configure Watermark Protection for bank 1 */
1627 FLASH->SECWM1R_PRG = ((WMSecEndSector << FLASH_SECWMR_SECWM_END_Pos) | WMSecStartSector);
1628 }
1629
1630 if ((Banks & FLASH_BANK_2) == FLASH_BANK_2)
1631 {
1632 /* Configure Watermark Protection for bank 2 */
1633 FLASH->SECWM2R_PRG = ((WMSecEndSector << FLASH_SECWMR_SECWM_END_Pos) | WMSecStartSector);
1634 }
1635 }
1636
1637 /**
1638 * @brief Return the watermark-based secure area configuration.
1639 *
1640 * @param Bank [in] specifies the bank where to get the watermark protection.
1641 * This parameter can be exclusively one of the following values:
1642 * @arg FLASH_BANK_1: Get bank1 watermark configuration
1643 * @arg FLASH_BANK_2: Get bank2 watermark configuration
1644 *
1645 * @param WMSecStartSector [out] specifies the start sector of the secure area
1646 *
1647 * @param WMSecEndSector [out] specifies the end sector of the secure area
1648 *
1649 * @retval None
1650 */
FLASH_OB_GetWMSEC(uint32_t Bank,uint32_t * WMSecStartSector,uint32_t * WMSecEndSector)1651 static void FLASH_OB_GetWMSEC(uint32_t Bank, uint32_t *WMSecStartSector, uint32_t *WMSecEndSector)
1652 {
1653 uint32_t regvalue = 0U;
1654
1655 /* Read SECWM register */
1656 if (Bank == FLASH_BANK_1)
1657 {
1658 regvalue = FLASH->SECWM1R_CUR;
1659 }
1660
1661 if (Bank == FLASH_BANK_2)
1662 {
1663 regvalue = FLASH->SECWM2R_CUR;
1664 }
1665
1666 /* Get configuration of secure area */
1667 *WMSecStartSector = (regvalue & FLASH_SECWMR_SECWM_STRT);
1668 *WMSecEndSector = ((regvalue & FLASH_SECWMR_SECWM_END) >> FLASH_SECWMR_SECWM_END_Pos);
1669 }
1670 #endif /* __ARM_FEATURE_CMSE */
1671
1672 /**
1673 * @brief Configure the hide protection area.
1674 *
1675 * @param Banks specifies the bank where to apply hide protection
1676 * This parameter can be one of the following values:
1677 * @arg FLASH_BANK_1: configure HDP on bank1
1678 * @arg FLASH_BANK_2: configure HDP on bank2
1679 * @arg FLASH_BANK_BOTH: configure HDP on both bank1 and bank2
1680 *
1681 * @param HDPStartSector specifies the start sector of the hide protection area
1682 * This parameter can be sector number between 0 and (max number of sectors in the bank - 1)
1683 *
1684 * @param HDPEndSector specifies the end sector of the hide protection area
1685 * This parameter can be sector number between HDPStartSector and HDPEndSector (max number of sectors
1686 * in the bank - 1)
1687 *
1688 * @retval None
1689 */
FLASH_OB_HDPConfig(uint32_t Banks,uint32_t HDPStartSector,uint32_t HDPEndSector)1690 static void FLASH_OB_HDPConfig(uint32_t Banks, uint32_t HDPStartSector, uint32_t HDPEndSector)
1691 {
1692 /* Check the parameters */
1693 assert_param(IS_FLASH_BANK(Banks));
1694 assert_param(IS_FLASH_SECTOR(HDPStartSector));
1695 assert_param(IS_FLASH_SECTOR(HDPEndSector));
1696
1697 /* Write HDP registers */
1698 if ((Banks & FLASH_BANK_1) == FLASH_BANK_1)
1699 {
1700 /* Configure hide Protection for bank 1 */
1701 FLASH->HDP1R_PRG = ((HDPEndSector << FLASH_HDPR_HDP_END_Pos) | HDPStartSector);
1702 }
1703
1704 if ((Banks & FLASH_BANK_2) == FLASH_BANK_2)
1705 {
1706 /* Configure hide Protection for bank 2 */
1707 FLASH->HDP2R_PRG = ((HDPEndSector << FLASH_HDPR_HDP_END_Pos) | HDPStartSector);
1708 }
1709 }
1710
1711 /**
1712 * @brief Return the hide protection area configuration.
1713 *
1714 * @param Bank [in] specifies the bank where to get the HDP protection.
1715 * This parameter can be exclusively one of the following values:
1716 * @arg FLASH_BANK_1: Get bank1 HDP configuration
1717 * @arg FLASH_BANK_2: Get bank2 HDP configuration
1718 *
1719 * @param HDPStartSector [out] specifies the start sector of the HDP area
1720 *
1721 * @param HDPEndSector [out] specifies the end sector of the HDP area
1722 *
1723 * @retval None
1724 */
FLASH_OB_GetHDP(uint32_t Bank,uint32_t * HDPStartSector,uint32_t * HDPEndSector)1725 static void FLASH_OB_GetHDP(uint32_t Bank, uint32_t *HDPStartSector, uint32_t *HDPEndSector)
1726 {
1727 uint32_t regvalue = 0U;
1728
1729 /* Read SECWM register */
1730 if (Bank == FLASH_BANK_1)
1731 {
1732 regvalue = FLASH->HDP1R_CUR;
1733 }
1734
1735 if (Bank == FLASH_BANK_2)
1736 {
1737 regvalue = FLASH->HDP2R_CUR;
1738 }
1739
1740 /* Get configuration of HDP area */
1741 *HDPStartSector = (regvalue & FLASH_HDPR_HDP_STRT);
1742 *HDPEndSector = ((regvalue & FLASH_HDPR_HDP_END) >> FLASH_HDPR_HDP_END_Pos);
1743 }
1744
1745 #if defined(FLASH_EDATAR_EDATA_EN)
1746 /**
1747 * @brief Configure the Flash high-cycle area.
1748 *
1749 * @param Banks specifies the bank where to apply Flash high-cycle data area
1750 * This parameter can be one of the following values:
1751 * @arg FLASH_BANK_1: configure Flash high-cycle area on bank1
1752 * @arg FLASH_BANK_2: configure Flash high-cycle area on bank2
1753 * @arg FLASH_BANK_BOTH: configure Flash high-cycle area on both bank1 and bank2
1754 *
1755 * @param EDATASize specifies the size (in sectors) of the Flash high-cycle data area
1756 * This parameter can be sectors number between 0 and 8
1757 * 0: Disable all EDATA sectors.
1758 * 1: The last sector is reserved for flash high-cycle data.
1759 * 2: The two last sectors are reserved for flash high-cycle data.
1760 * 3: The three last sectors are reserved for flash high-cycle data
1761 * 4: The four last sectors is reserved for flash high-cycle data.
1762 * 5: The five last sectors are reserved for flash high-cycle data.
1763 * 6: The six last sectors are reserved for flash high-cycle data.
1764 * 7: The seven last sectors are reserved for flash high-cycle data.
1765 * 8: The eight last sectors are reserved for flash high-cycle data.
1766 *
1767 * @retval None
1768 */
FLASH_OB_EDATAConfig(uint32_t Banks,uint32_t EDATASize)1769 static void FLASH_OB_EDATAConfig(uint32_t Banks, uint32_t EDATASize)
1770 {
1771 /* Check the parameters */
1772 assert_param(IS_FLASH_BANK(Banks));
1773 assert_param(IS_FLASH_EDATA_SIZE(EDATASize));
1774
1775 if (EDATASize != 0U)
1776 {
1777 /* Write EDATA registers */
1778 if ((Banks & FLASH_BANK_1) == FLASH_BANK_1)
1779 {
1780 /* Configure Flash high-cycle data for bank 1 */
1781 FLASH->EDATA1R_PRG = (FLASH_EDATAR_EDATA_EN | (EDATASize - 1U));
1782 }
1783
1784 if ((Banks & FLASH_BANK_2) == FLASH_BANK_2)
1785 {
1786 /* Configure Flash high-cycle data for bank 2 */
1787 FLASH->EDATA2R_PRG = (FLASH_EDATAR_EDATA_EN | (EDATASize - 1U));
1788 }
1789 }
1790 else
1791 {
1792 /* Write EDATA registers */
1793 if ((Banks & FLASH_BANK_1) == FLASH_BANK_1)
1794 {
1795 /* Disable Flash high-cycle data for bank 1 */
1796 FLASH->EDATA1R_PRG = 0U;
1797 }
1798
1799 if ((Banks & FLASH_BANK_2) == FLASH_BANK_2)
1800 {
1801 /* Disable Flash high-cycle data for bank 2 */
1802 FLASH->EDATA2R_PRG = 0U;
1803 }
1804 }
1805 }
1806
1807 /**
1808 * @brief Return the Flash high-cycle data area configuration.
1809 *
1810 * @param Bank [in] specifies the bank where to get the Flash high-cycle data configuration.
1811 * This parameter can be exclusively one of the following values:
1812 * @arg FLASH_BANK_1: Get bank1 Flash high-cycle data configuration
1813 * @arg FLASH_BANK_2: Get bank2 Flash high-cycle data configuration
1814 *
1815 * @param EDATASize [out] specifies the size (in sectors) of the Flash high-cycle data area
1816 *
1817 * @retval None
1818 */
FLASH_OB_GetEDATA(uint32_t Bank,uint32_t * EDATASize)1819 static void FLASH_OB_GetEDATA(uint32_t Bank, uint32_t *EDATASize)
1820 {
1821 uint32_t regvalue = 0U;
1822
1823 /* Read SECWM register */
1824 if (Bank == FLASH_BANK_1)
1825 {
1826 regvalue = FLASH->EDATA1R_CUR;
1827 }
1828
1829 if (Bank == FLASH_BANK_2)
1830 {
1831 regvalue = FLASH->EDATA2R_CUR;
1832 }
1833
1834 /* Get configuration of secure area */
1835 if ((regvalue & FLASH_EDATAR_EDATA_EN) != 0U)
1836 {
1837 /* Encoding of Edata Area size is register value + 1 */
1838 *EDATASize = (regvalue & FLASH_EDATAR_EDATA_STRT) + 1U;
1839 }
1840 else
1841 {
1842 /* No defined Edata area */
1843 *EDATASize = 0U;
1844 }
1845
1846 }
1847 #endif /* FLASH_EDATAR_EDATA_EN */
1848
1849 /**
1850 * @}
1851 */
1852
1853 /** @defgroup FLASHEx_Exported_Functions_Group3 Extended ECC operation functions
1854 * @brief Extended ECC operation functions
1855 *
1856 @verbatim
1857 ===============================================================================
1858 ##### Extended ECC operation functions #####
1859 ===============================================================================
1860 [..]
1861 This subsection provides a set of functions allowing to manage the Extended FLASH
1862 ECC Operations.
1863
1864 @endverbatim
1865 * @{
1866 */
1867 /**
1868 * @brief Enable ECC correction interrupt
1869 * @param None
1870 * @retval None
1871 */
HAL_FLASHEx_EnableEccCorrectionInterrupt(void)1872 void HAL_FLASHEx_EnableEccCorrectionInterrupt(void)
1873 {
1874 __HAL_FLASH_ENABLE_IT(FLASH_IT_ECCC);
1875 }
1876
1877 /**
1878 * @brief Disable ECC correction interrupt
1879 * @param None
1880 * @retval None
1881 */
HAL_FLASHEx_DisableEccCorrectionInterrupt(void)1882 void HAL_FLASHEx_DisableEccCorrectionInterrupt(void)
1883 {
1884 __HAL_FLASH_DISABLE_IT(FLASH_IT_ECCC);
1885 }
1886
1887 /**
1888 * @brief Get the ECC error information.
1889 * @param pData Pointer to an FLASH_EccInfoTypeDef structure that contains the
1890 * ECC error information.
1891 * @note This function should be called before ECC bit is cleared
1892 * (in callback function)
1893 * @retval None
1894 */
HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef * pData)1895 void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData)
1896 {
1897 uint32_t correction_reg = FLASH->ECCCORR;
1898 uint32_t detection_reg = FLASH->ECCDETR;
1899 uint32_t data_reg = FLASH->ECCDR;
1900 uint32_t addr_reg = 0xFFFFFFFFU;
1901
1902 /* Check if the operation is a correction or a detection*/
1903 if ((correction_reg & FLASH_ECCR_ECCC) != 0U)
1904 {
1905 /* Get area and offset address values from ECCCORR register*/
1906 pData->Area = correction_reg & (~(FLASH_ECCR_ECCIE | FLASH_ECCR_ADDR_ECC | FLASH_ECCR_ECCC));
1907 addr_reg = (correction_reg & FLASH_ECCR_ADDR_ECC);
1908 }
1909 else if ((detection_reg & FLASH_ECCR_ECCD) != 0U)
1910 {
1911 /* Get area and offset address values from ECCDETR register */
1912 pData->Area = detection_reg & (~(FLASH_ECCR_ADDR_ECC | FLASH_ECCR_ECCD));
1913 addr_reg = (detection_reg & FLASH_ECCR_ADDR_ECC);
1914 }
1915 else
1916 {
1917 /* Do nothing */
1918 }
1919
1920 /* Check that an ECC single or double error has occurred to continue the calculation of area address */
1921 if (addr_reg != 0xFFFFFFFFU)
1922 {
1923 /* Get address value according to area value*/
1924 switch (pData->Area)
1925 {
1926 case FLASH_ECC_AREA_USER_BANK1:
1927 /*
1928 * One error detection/correction or two error detections per 128-bit flash word
1929 * Therefore, the address returned by ECC registers in bank1 represents 128-bit flash word,
1930 * to get the correct address value, we must do a shift by 4 bits
1931 */
1932 addr_reg = addr_reg << 4U;
1933 pData->Address = FLASH_BASE + addr_reg;
1934 break;
1935 case FLASH_ECC_AREA_USER_BANK2:
1936 /*
1937 * One error detection/correction or two error detections per 128-bit flash word
1938 * Therefore, the address returned by ECC registers in bank2 represents 128-bit flash word,
1939 * to get the correct address value, we must do a shift by 4 bits
1940 */
1941 addr_reg = addr_reg << 4U;
1942 pData->Address = FLASH_BASE + FLASH_BANK_SIZE + addr_reg;
1943 break;
1944 case FLASH_ECC_AREA_SYSTEM:
1945 /* check system flash bank */
1946 if ((correction_reg & FLASH_ECCR_BK_ECC) == FLASH_ECCR_BK_ECC)
1947 {
1948 pData->Address = FLASH_SYSTEM_BASE + FLASH_SYSTEM_SIZE + addr_reg;
1949 }
1950 else
1951 {
1952 pData->Address = FLASH_SYSTEM_BASE + addr_reg;
1953 }
1954 break;
1955 #if defined (FLASH_SR_OBKERR)
1956 case FLASH_ECC_AREA_OBK:
1957 pData->Address = FLASH_OBK_BASE + addr_reg;
1958 break;
1959 #endif /* FLASH_SR_OBKERR */
1960 #if defined (FLASH_EDATAR_EDATA_EN)
1961 case FLASH_ECC_AREA_EDATA:
1962 /* check flash high-cycle data bank */
1963 if ((correction_reg & FLASH_ECCR_BK_ECC) == FLASH_ECCR_BK_ECC)
1964 {
1965 /*
1966 * addr_reg is the address returned by the ECC register along with an offset value depends on area
1967 * To calculate the exact address set by user while an ECC occurred, we must subtract the offset value,
1968 * In addition, the address returned by ECC registers represents 128-bit flash word (multiply by 4),
1969 */
1970 pData->Address = FLASH_EDATA_BASE + FLASH_BANK_SIZE + ((addr_reg - FLASH_ADDRESS_OFFSET_EDATA) * 4U);
1971 }
1972 else
1973 {
1974 pData->Address = FLASH_EDATA_BASE + ((addr_reg - FLASH_ADDRESS_OFFSET_EDATA) * 4U);
1975 }
1976 break;
1977 #endif /* FLASH_EDATAR_EDATA_EN */
1978 case FLASH_ECC_AREA_OTP:
1979 /* Address returned by the ECC is an halfword, multiply by 4 to get the exact address*/
1980 pData->Address = FLASH_OTP_BASE + ((addr_reg - FLASH_ADDRESS_OFFSET_OTP) * 4U);
1981 break;
1982
1983 default:
1984 /* Do nothing */
1985 break;
1986 }
1987 }
1988
1989 pData->Data = data_reg & FLASH_ECCR_ADDR_ECC;
1990 }
1991
1992 /**
1993 * @brief Handle Flash ECC Detection interrupt request.
1994 * @retval None
1995 */
HAL_FLASHEx_ECCD_IRQHandler(void)1996 void HAL_FLASHEx_ECCD_IRQHandler(void)
1997 {
1998 /* Check if the ECC double error occurred*/
1999 if (READ_BIT(FLASH->ECCDETR, FLASH_ECCR_ECCD) != 0U)
2000 {
2001 /* FLASH ECC detection user callback */
2002 HAL_FLASHEx_EccDetectionCallback();
2003
2004 /* Clear ECCD flag
2005 note : this step will clear all the information related to the flash ecc detection
2006 */
2007 SET_BIT(FLASH->ECCDETR, FLASH_ECCR_ECCD);
2008 }
2009 }
2010
2011 /**
2012 * @brief FLASH ECC Correction interrupt callback.
2013 * @retval None
2014 */
HAL_FLASHEx_EccCorrectionCallback(void)2015 __weak void HAL_FLASHEx_EccCorrectionCallback(void)
2016 {
2017 /* NOTE : This function should not be modified, when the callback is needed,
2018 the HAL_FLASHEx_EccCorrectionCallback could be implemented in the user file
2019 */
2020 }
2021
2022 /**
2023 * @brief FLASH ECC Detection interrupt callback.
2024 * @retval None
2025 */
HAL_FLASHEx_EccDetectionCallback(void)2026 __weak void HAL_FLASHEx_EccDetectionCallback(void)
2027 {
2028 /* NOTE : This function should not be modified, when the callback is needed,
2029 the HAL_FLASHEx_EccDetectionCallback could be implemented in the user file
2030 */
2031 }
2032
2033 /**
2034 * @}
2035 */
2036
2037 /**
2038 * @}
2039 */
2040 #endif /* HAL_FLASH_MODULE_ENABLED */
2041
2042 /**
2043 * @}
2044 */
2045
2046 /**
2047 * @}
2048 */
2049
