290                                      FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)  in FMC_NORSRAM_DeInit()  argument
295   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_DeInit()
298   __FMC_NORSRAM_DISABLE(Device, Bank);  in FMC_NORSRAM_DeInit()
302   if (Bank == FMC_NORSRAM_BANK1)  in FMC_NORSRAM_DeInit()
304     Device->BTCR[Bank] = 0x000030DBU;  in FMC_NORSRAM_DeInit()
309     Device->BTCR[Bank] = 0x000030D2U;  in FMC_NORSRAM_DeInit()
312   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
313   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
327                                           FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NORSRAM_Timing_Init()  argument
340   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Timing_Init()
343   Device->BTCR[Bank + 1U] =  in FMC_NORSRAM_Timing_Init()
376                                                    FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,  in FMC_NORSRAM_Extended_Timing_Init()  argument
391     assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Extended_Timing_Init()
394 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
401     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FMC_NORSRAM_Extended_Timing_Init()
431 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Enable()  argument
435   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Enable()
438   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Enable()
449 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Disable()  argument
453   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Disable()
456   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Disable()
569 …                                                 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_CommonSpace_Timing_Init()  argument
577   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_CommonSpace_Timing_Init()
580   if (Bank == FMC_NAND_BANK2)  in FMC_NAND_CommonSpace_Timing_Init()
609 …                                                 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_AttributeSpace_Timing_Init()  argument
617   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_AttributeSpace_Timing_Init()
620   if (Bank == FMC_NAND_BANK2)  in FMC_NAND_AttributeSpace_Timing_Init()
646 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_DeInit()  argument
650   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_DeInit()
653   __FMC_NAND_DISABLE(Device, Bank);  in FMC_NAND_DeInit()
656   if (Bank == FMC_NAND_BANK2)  in FMC_NAND_DeInit()
703 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Enable()  argument
707   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Enable()
710   if (Bank == FMC_NAND_BANK2)  in FMC_NAND_ECC_Enable()
729 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Disable()  argument
733   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Disable()
736   if (Bank == FMC_NAND_BANK2)  in FMC_NAND_ECC_Disable()
756 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FMC_NAND_GetECC()  argument
763   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_GetECC()
769   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)  in FMC_NAND_GetECC()
781   if (Bank == FMC_NAND_BANK2)  in FMC_NAND_GetECC()