276                                       FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)  in FSMC_NORSRAM_DeInit()  argument
281   assert_param(IS_FSMC_NORSRAM_BANK(Bank));  in FSMC_NORSRAM_DeInit()
284   __FSMC_NORSRAM_DISABLE(Device, Bank);  in FSMC_NORSRAM_DeInit()
288   if (Bank == FSMC_NORSRAM_BANK1)  in FSMC_NORSRAM_DeInit()
290     Device->BTCR[Bank] = 0x000030DBU;  in FSMC_NORSRAM_DeInit()
295     Device->BTCR[Bank] = 0x000030D2U;  in FSMC_NORSRAM_DeInit()
298   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FSMC_NORSRAM_DeInit()
299   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;  in FSMC_NORSRAM_DeInit()
313                                            const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)  in FSMC_NORSRAM_Timing_Init()  argument
325   assert_param(IS_FSMC_NORSRAM_BANK(Bank));  in FSMC_NORSRAM_Timing_Init()
328   Device->BTCR[Bank + 1U] =  in FSMC_NORSRAM_Timing_Init()
353 …                                           const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,  in FSMC_NORSRAM_Extended_Timing_Init()  argument
369     assert_param(IS_FSMC_NORSRAM_BANK(Bank));  in FSMC_NORSRAM_Extended_Timing_Init()
372 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FSMC_NORSRAM_Extended_Timing_Init()
380     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FSMC_NORSRAM_Extended_Timing_Init()
410 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FSMC_NORSRAM_WriteOperation_Enable()  argument
414   assert_param(IS_FSMC_NORSRAM_BANK(Bank));  in FSMC_NORSRAM_WriteOperation_Enable()
417   SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);  in FSMC_NORSRAM_WriteOperation_Enable()
428 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FSMC_NORSRAM_WriteOperation_Disable()  argument
432   assert_param(IS_FSMC_NORSRAM_BANK(Bank));  in FSMC_NORSRAM_WriteOperation_Disable()
435   CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);  in FSMC_NORSRAM_WriteOperation_Disable()
546 …                                          const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FSMC_NAND_CommonSpace_Timing_Init()  argument
554   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_CommonSpace_Timing_Init()
557   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_CommonSpace_Timing_Init()
586 …                                          const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FSMC_NAND_AttributeSpace_Timing_Init()  argument
594   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_AttributeSpace_Timing_Init()
597   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_AttributeSpace_Timing_Init()
623 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_DeInit()  argument
627   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_DeInit()
630   __FSMC_NAND_DISABLE(Device, Bank);  in FSMC_NAND_DeInit()
633   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_DeInit()
680 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_ECC_Enable()  argument
684   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_ECC_Enable()
687   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_ECC_Enable()
706 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_ECC_Disable()  argument
710   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_ECC_Disable()
713   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_ECC_Disable()
733 HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FSMC_NAND_GetECC()  argument
740   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_GetECC()
746   while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)  in FSMC_NAND_GetECC()
758   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_GetECC()