362                                      FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)  in FMC_NORSRAM_DeInit()  argument
367   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_DeInit()
370   __FMC_NORSRAM_DISABLE(Device, Bank);  in FMC_NORSRAM_DeInit()
374   if (Bank == FMC_NORSRAM_BANK1)  in FMC_NORSRAM_DeInit()
376     Device->BTCR[Bank] = 0x000030DBU;  in FMC_NORSRAM_DeInit()
381     Device->BTCR[Bank] = 0x000030D2U;  in FMC_NORSRAM_DeInit()
384   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
385   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
399                                           FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NORSRAM_Timing_Init()  argument
414   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Timing_Init()
417 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                     …  in FMC_NORSRAM_Timing_Init()
451                                                    FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,  in FMC_NORSRAM_Extended_Timing_Init()  argument
467     assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Extended_Timing_Init()
470 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
478     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FMC_NORSRAM_Extended_Timing_Init()
508 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Enable()  argument
512   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Enable()
515   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Enable()
526 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Disable()  argument
530   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Disable()
533   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Disable()
657 …                                                 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_CommonSpace_Timing_Init()  argument
665   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_CommonSpace_Timing_Init()
669   if (Bank == FMC_NAND_BANK2)  in FMC_NAND_CommonSpace_Timing_Init()
687   UNUSED(Bank);  in FMC_NAND_CommonSpace_Timing_Init()
708 …                                                 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_AttributeSpace_Timing_Init()  argument
716   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_AttributeSpace_Timing_Init()
720   if (Bank == FMC_NAND_BANK2)  in FMC_NAND_AttributeSpace_Timing_Init()
738   UNUSED(Bank);  in FMC_NAND_AttributeSpace_Timing_Init()
756 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_DeInit()  argument
760   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_DeInit()
763   __FMC_NAND_DISABLE(Device, Bank);  in FMC_NAND_DeInit()
767   if (Bank == FMC_NAND_BANK2)  in FMC_NAND_DeInit()
786   UNUSED(Bank);  in FMC_NAND_DeInit()
824 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Enable()  argument
828   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Enable()
832   if (Bank == FMC_NAND_BANK2)  in FMC_NAND_ECC_Enable()
842   UNUSED(Bank);  in FMC_NAND_ECC_Enable()
857 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Disable()  argument
861   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Disable()
865   if (Bank == FMC_NAND_BANK2)  in FMC_NAND_ECC_Disable()
875   UNUSED(Bank);  in FMC_NAND_ECC_Disable()
891 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FMC_NAND_GetECC()  argument
898   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_GetECC()
904   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)  in FMC_NAND_GetECC()
917   if (Bank == FMC_NAND_BANK2)  in FMC_NAND_GetECC()
929   UNUSED(Bank);  in FMC_NAND_GetECC()
1244                                         FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)  in FMC_SDRAM_Timing_Init()  argument
1255   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_Timing_Init()
1258   if (Bank == FMC_SDRAM_BANK1)  in FMC_SDRAM_Timing_Init()
1295 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_DeInit()  argument
1299   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_DeInit()
1302   Device->SDCR[Bank] = 0x000002D0U;  in FMC_SDRAM_DeInit()
1303   Device->SDTR[Bank] = 0x0FFFFFFFU;  in FMC_SDRAM_DeInit()
1336 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_WriteProtection_Enable()  argument
1340   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_WriteProtection_Enable()
1343   SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);  in FMC_SDRAM_WriteProtection_Enable()
1353 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_WriteProtection_Disable()  argument
1357   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_WriteProtection_Disable()
1360   CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);  in FMC_SDRAM_WriteProtection_Disable()
1453 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_GetModeStatus()  argument
1459   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_GetModeStatus()
1462   if (Bank == FMC_SDRAM_BANK1)  in FMC_SDRAM_GetModeStatus()