329                                      FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)  in FMC_NORSRAM_DeInit()  argument
334   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_DeInit()
337   __FMC_NORSRAM_DISABLE(Device, Bank);  in FMC_NORSRAM_DeInit()
341   if (Bank == FMC_NORSRAM_BANK1)  in FMC_NORSRAM_DeInit()
343     Device->BTCR[Bank] = 0x000030DBU;  in FMC_NORSRAM_DeInit()
348     Device->BTCR[Bank] = 0x000030D2U;  in FMC_NORSRAM_DeInit()
351   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
352   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
355   switch (Bank)  in FMC_NORSRAM_DeInit()
386                                           const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NORSRAM_Timing_Init()  argument
400   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Timing_Init()
403   Device->BTCR[Bank + 1U] =  in FMC_NORSRAM_Timing_Init()
437 …                                            const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,  in FMC_NORSRAM_Extended_Timing_Init()  argument
454     assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Extended_Timing_Init()
457 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
466     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FMC_NORSRAM_Extended_Timing_Init()
496 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Enable()  argument
500   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Enable()
503   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Enable()
514 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Disable()  argument
518   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Disable()
521   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Disable()
619 …                                           const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_CommonSpace_Timing_Init()  argument
627   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_CommonSpace_Timing_Init()
630   UNUSED(Bank);  in FMC_NAND_CommonSpace_Timing_Init()
650 …                                           const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_AttributeSpace_Timing_Init()  argument
658   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_AttributeSpace_Timing_Init()
661   UNUSED(Bank);  in FMC_NAND_AttributeSpace_Timing_Init()
678 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_DeInit()  argument
682   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_DeInit()
685   __FMC_NAND_DISABLE(Device, Bank);  in FMC_NAND_DeInit()
689   UNUSED(Bank);  in FMC_NAND_DeInit()
726 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Enable()  argument
730   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Enable()
734   UNUSED(Bank);  in FMC_NAND_ECC_Enable()
748 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Disable()  argument
752   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Disable()
756   UNUSED(Bank);  in FMC_NAND_ECC_Disable()
771 HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FMC_NAND_GetECC()  argument
778   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_GetECC()
784   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)  in FMC_NAND_GetECC()
797   UNUSED(Bank);  in FMC_NAND_GetECC()
922                                         const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)  in FMC_SDRAM_Timing_Init()  argument
933   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_Timing_Init()
936   if (Bank == FMC_SDRAM_BANK1)  in FMC_SDRAM_Timing_Init()
973 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_DeInit()  argument
977   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_DeInit()
980   Device->SDCR[Bank] = 0x000002D0U;  in FMC_SDRAM_DeInit()
981   Device->SDTR[Bank] = 0x0FFFFFFFU;  in FMC_SDRAM_DeInit()
1014 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_WriteProtection_Enable()  argument
1018   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_WriteProtection_Enable()
1021   SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);  in FMC_SDRAM_WriteProtection_Enable()
1031 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_WriteProtection_Disable()  argument
1035   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_WriteProtection_Disable()
1038   CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);  in FMC_SDRAM_WriteProtection_Disable()
1117 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_GetModeStatus()  argument
1123   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_GetModeStatus()
1126   if (Bank == FMC_SDRAM_BANK1)  in FMC_SDRAM_GetModeStatus()