292                                       FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)  in FSMC_NORSRAM_DeInit()  argument
297   assert_param(IS_FSMC_NORSRAM_BANK(Bank));  in FSMC_NORSRAM_DeInit()
300   __FSMC_NORSRAM_DISABLE(Device, Bank);  in FSMC_NORSRAM_DeInit()
304   if (Bank == FSMC_NORSRAM_BANK1)  in FSMC_NORSRAM_DeInit()
306     Device->BTCR[Bank] = 0x000030DBU;  in FSMC_NORSRAM_DeInit()
311     Device->BTCR[Bank] = 0x000030D2U;  in FSMC_NORSRAM_DeInit()
314   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FSMC_NORSRAM_DeInit()
315   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;  in FSMC_NORSRAM_DeInit()
329                                            const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)  in FSMC_NORSRAM_Timing_Init()  argument
341   assert_param(IS_FSMC_NORSRAM_BANK(Bank));  in FSMC_NORSRAM_Timing_Init()
344   Device->BTCR[Bank + 1U] =  in FSMC_NORSRAM_Timing_Init()
369 …                                           const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,  in FSMC_NORSRAM_Extended_Timing_Init()  argument
390     assert_param(IS_FSMC_NORSRAM_BANK(Bank));  in FSMC_NORSRAM_Extended_Timing_Init()
394 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FSMC_NORSRAM_Extended_Timing_Init()
400 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FSMC_NORSRAM_Extended_Timing_Init()
410     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FSMC_NORSRAM_Extended_Timing_Init()
440 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FSMC_NORSRAM_WriteOperation_Enable()  argument
444   assert_param(IS_FSMC_NORSRAM_BANK(Bank));  in FSMC_NORSRAM_WriteOperation_Enable()
447   SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);  in FSMC_NORSRAM_WriteOperation_Enable()
458 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FSMC_NORSRAM_WriteOperation_Disable()  argument
462   assert_param(IS_FSMC_NORSRAM_BANK(Bank));  in FSMC_NORSRAM_WriteOperation_Disable()
465   CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);  in FSMC_NORSRAM_WriteOperation_Disable()
578 …                                          const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FSMC_NAND_CommonSpace_Timing_Init()  argument
586   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_CommonSpace_Timing_Init()
589   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_CommonSpace_Timing_Init()
618 …                                          const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FSMC_NAND_AttributeSpace_Timing_Init()  argument
626   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_AttributeSpace_Timing_Init()
629   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_AttributeSpace_Timing_Init()
655 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_DeInit()  argument
659   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_DeInit()
662   __FSMC_NAND_DISABLE(Device, Bank);  in FSMC_NAND_DeInit()
665   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_DeInit()
712 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_ECC_Enable()  argument
716   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_ECC_Enable()
719   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_ECC_Enable()
738 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_ECC_Disable()  argument
742   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_ECC_Disable()
745   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_ECC_Disable()
765 HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FSMC_NAND_GetECC()  argument
772   assert_param(IS_FSMC_NAND_BANK(Bank));  in FSMC_NAND_GetECC()
778   while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)  in FSMC_NAND_GetECC()
790   if (Bank == FSMC_NAND_BANK2)  in FSMC_NAND_GetECC()