293                                      FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)  in FMC_NORSRAM_DeInit()  argument
298   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_DeInit()
301   __FMC_NORSRAM_DISABLE(Device, Bank);  in FMC_NORSRAM_DeInit()
305   if (Bank == FMC_NORSRAM_BANK1)  in FMC_NORSRAM_DeInit()
307     Device->BTCR[Bank] = 0x000030DBU;  in FMC_NORSRAM_DeInit()
312     Device->BTCR[Bank] = 0x000030D2U;  in FMC_NORSRAM_DeInit()
315   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
316   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
330                                           const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NORSRAM_Timing_Init()  argument
343   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Timing_Init()
346   Device->BTCR[Bank + 1U] =  in FMC_NORSRAM_Timing_Init()
379 …                                            const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,  in FMC_NORSRAM_Extended_Timing_Init()  argument
397     assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_Extended_Timing_Init()
401 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
407 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
415     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FMC_NORSRAM_Extended_Timing_Init()
445 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Enable()  argument
449   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Enable()
452   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Enable()
463 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Disable()  argument
467   assert_param(IS_FMC_NORSRAM_BANK(Bank));  in FMC_NORSRAM_WriteOperation_Disable()
470   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Disable()
566 …                                           const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_CommonSpace_Timing_Init()  argument
574   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_CommonSpace_Timing_Init()
577   UNUSED(Bank);  in FMC_NAND_CommonSpace_Timing_Init()
597 …                                           const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)  in FMC_NAND_AttributeSpace_Timing_Init()  argument
605   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_AttributeSpace_Timing_Init()
608   UNUSED(Bank);  in FMC_NAND_AttributeSpace_Timing_Init()
625 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_DeInit()  argument
629   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_DeInit()
632   __FMC_NAND_DISABLE(Device, Bank);  in FMC_NAND_DeInit()
636   UNUSED(Bank);  in FMC_NAND_DeInit()
673 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Enable()  argument
677   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Enable()
681   UNUSED(Bank);  in FMC_NAND_ECC_Enable()
695 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Disable()  argument
699   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_ECC_Disable()
703   UNUSED(Bank);  in FMC_NAND_ECC_Disable()
718 HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FMC_NAND_GetECC()  argument
725   assert_param(IS_FMC_NAND_BANK(Bank));  in FMC_NAND_GetECC()
731   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)  in FMC_NAND_GetECC()
744   UNUSED(Bank);  in FMC_NAND_GetECC()
866                                         const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)  in FMC_SDRAM_Timing_Init()  argument
877   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_Timing_Init()
880   if (Bank == FMC_SDRAM_BANK1)  in FMC_SDRAM_Timing_Init()
917 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_DeInit()  argument
921   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_DeInit()
924   Device->SDCR[Bank] = 0x000002D0U;  in FMC_SDRAM_DeInit()
925   Device->SDTR[Bank] = 0x0FFFFFFFU;  in FMC_SDRAM_DeInit()
958 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_WriteProtection_Enable()  argument
962   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_WriteProtection_Enable()
965   SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);  in FMC_SDRAM_WriteProtection_Enable()
975 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_WriteProtection_Disable()  argument
979   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_WriteProtection_Disable()
982   CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);  in FMC_SDRAM_WriteProtection_Disable()
1061 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_GetModeStatus()  argument
1067   assert_param(IS_FMC_SDRAM_BANK(Bank));  in FMC_SDRAM_GetModeStatus()
1070   if (Bank == FMC_SDRAM_BANK1)  in FMC_SDRAM_GetModeStatus()